S E M I C O N D U C T O R
HI3026, CXA3026Q
8-Bit 120 MSPS Flash A/D Converter
Description
The HI3026, CXA3026Q is an 8-bit ultra high-speed flash
A/D converter capable of digitizing analog signals at the
maximum rate of 120 MSPS. ECL, PECL or TTL can be
selected as the digital input level in accordance with the
application. The TTL digital output level allows 1:2 demulti-
plexed output.
December 1996
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Differential Linearity Error
. . . . . . . . . . . . . . . . . ±0.5
LSB
Integral Linearity Error . . . . . . . . . . . . . . . . . .
±0.5
LSB
Integral Linearity Compensation Circuit
Ultra High-Speed Operation with a Maximum Conversion
Rate of 120 MSPS
Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . 21pF
Wide Analog Input Bandwidth . . . . . . . . . . . . . 200MHz
Low Power Consumption . . . . . . . . . . . . . . . . . .640mW
Low Error Rate
Excellent Temperature Characteristics
Internal 1/2 Frequency Divider Circuit (w/Reset Function)
CLK/2 Clock Output
Compatible with ECL, PECL and TTL Digital Input Levels
1:2 Demultiplexed Output
Surface Mounting Package
Ordering Information
PART
NUMBER
HI3026JCQ
CXA3026Q
TEMP. RANGE
(
o
C)
-20 to 75
-20 to 75
PACKAGE
48 Ld MQFP
48 Ld MQFP
PKG. NO.
Q48.12x12-S
Q48.12x12-S
Applications
•
•
•
•
Magnetic Recording (PRML)
Communications (QPSK, QAM)
LCDs
Digital Oscilloscopes
HI3026, CXA3026Q
(MQFP)
TOP VIEW
NRSET/E
NRSETN/E
NRSET/T
SELECT
INV
CLKOUT
DV
CC2
DGND2
Pinout
P1D7
P1D6
P1D5
DV
EE3
V
RB
AGND
V
RM1
AV
CC
V
IN
V
RM2
AV
CC
V
RM3
AGND
V
RT
DGND3
1
2
3
4
5
6
7
8
9
10
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
P1D4
P1D3
P1D2
P1D1
P1D0
DGND2
DV
CC2
DV
CC1
DGND1
P2D7
P2D6
P2D5
P2D4
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
DV
CC2
DGND2
CLK/T
NC
CLKN/E
P2D0
P2D1
NC
NC
P2D2
CLK/E
P2D3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1996
File Number
4109.2
1
HI3026, CXA3026Q
Block Diagram
2
HI3026, CXA3026Q
Pin Descriptions
TYPICAL
VOLTAGE
LEVEL
GND
PIN NO
3, 10
SYMBOL
AGND
I/O
EQUIVALENT CIRCUIT
DESCRIPTION
Analog ground. Separated from the digital
ground
Analog power supply. Separated from the
digital power supply.
Digital ground.
5, 8
AV
CC
DGND1
DGND2
DV
CC1
DV
CC2
DGND3
+5V (Typ)
20, 29
32, 41
19, 30
31, 42
12
GND
+5V (Typ)
Digital power supply
+5V (Typ) (With
a single power
Supply)
GND (With dual
power supplies)
Digital power supply. Ground for ECL
input. -5V for PECL and TTL input.
1
DV
EE
3
GND (With a
single power
supply)
+5V (Typ) (With
dual power
supplies)
Digital power supply. Ground for ECL
input.-5V for PECL and TTL input.
16, 17,
18
13
14
NC
No connected pin. Not connected with the
internal circuits.
I
I
ECL/PECL
Clock input.
CLK/E complementary input. When left
open, this pin goes to the threshold poten-
tial. Only CLK/E can be used for operation,
but complementary input is recommended
to attain fast and stable operation.
Reset input. When the input is set to low
level, the built-in CLK frequency divider cir-
cuit can be reset.
RESETN/E complementary input. When left
open, this pin goes to the threshold voltage.
Only RESETN/E can be used for operation.
TTL
Clock input.
Reset input. When left open, this input
goes to high level. When the input is set to
low level, the built-in CLK frequency divid-
er circuit can be reset.
CLK/E
CLK/NE
48
RE-
SETN/E
I
47
RESET/E
I
15
46
CLK/T
RESETN/T
I
I
3
HI3026, CXA3026Q
Pin Descriptions
(Continued)
TYPICAL
VOLTAGE
LEVEL
TTL
PIN NO
44
SYMBOL
INV
I/O
I
EQUIVALENT CIRCUIT
DESCRIPTION
Data output polarity inversion input. When
left open, this input goes to high level.
(See Table 1. I/O Correspondence Table.)
45
SELECT
V
CC
or GND
Data output mode selection. (See Table 2.
Operating Mode Table.)
11
V
RT
I
4.0V (Typ)
Top reference voltage. By-pass to AGND
with a 1µF tantal capacitor and a 0.1µF
chip capacitor.
Reference voltage mid point. By-pass to
AGND with a 0.1µF chip capacitor.
Reference voltage mid point. By-pass to
AGND with a 0.1µF chip capacitor.
Reference voltage mid point. By-pass to
AGND with a 0.1µF chip capacitor.
Bottom reference voltage. By-pass to
AGND with a 1µF tantal capacitor and a
0.1µF chip capacitor.
9
V
RM3
V
RB
+
3
--
(V
RT
- V
RB
)
-
4
V
RB
+
2
--
(V
RT
- V
RB
)
-
4
V
RB
+
1
--
(V
RT
- V
RB
)
-
4
I
2.0V (Typ)
7
V
RM
2
4
V
RM1
VRB
2
4
HI3026, CXA3026Q
Pin Descriptions
(Continued)
TYPICAL
VOLTAGE
LEVEL
V
RT
to V
RB
PIN NO
6
SYMBOL
V
IN
I/O
I
EQUIVALENT CIRCUIT
DESCRIPTION
Analog input.
33 to 40
P1D0 to
P1D7
P2D0 to
P2D7
CLKOUT
O
TTL
Port 1 side data output.
21 to 28
O
Port 2 side data output.
43
O
Clock output. (See Table 2. Operating
Mode Table.)
5
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