HD74LV393A
Dual 4-bit Binary Counters
REJ03D0333–0300Z
(Previous ADE-205-276A (Z))
Rev.3.00
Jun. 28, 2004
Description
The HD74LV393A contain two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-
256 counter.
The HD74LV393A is incremented on the high to low transition (negative edge) of the clock input, and each has an
independent clear input. When clear is set high all four bits of each counter is set to a low level. This enables count
truncation and allows the implementation of divide-by-N counter configurations.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the
low-power consumption extends the battery life.
Features
•
•
•
•
•
•
•
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25°C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25°C)
Output current ±6 mA (@V
CC
= 3.0 V to 3.6 V), ±12 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP–14 pin(JEITA)
SOP–14 pin(JEDEC)
TSSOP–14 pin
Package Code
FP–14DAV
FP–14DNV
TTP–14DV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV393AFPEL
HD74LV393ARPEL
HD74LV393ATELL
Note: Please consult the sales office for the above package availability.
Rev.3.00 Jun. 28, 2004 page 1 of 10
HD74LV393A
Function Table
Inputs
CLK
X
H
L
↑
↓
Note: H:
L:
X:
↑:
↓:
High level
Low level
Immaterial
Low to high transition
High to low transition
CLR
H
L
L
L
L
Output
L
No change
No change
No change
Count up
Pin Arrangement
1CLK 1
1CLR 2
1QA 3
1QB 4
1QC 5
1QD 6
GND 7
14 V
CC
13 2CLK
12 2CLR
11 2QA
10 2QB
9 2QC
8 2QD
(Top view)
Rev.3.00 Jun. 28, 2004 page 2 of 10
HD74LV393A
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range*
Output voltage range*
1, 2
Input clamp current
Output clamp current
Continuous output current
Continuous current through
V
CC
or GND
Maximum power dissipation at
Ta = 25°C (in still air)*
3
Storage temperature
1
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
or
I
GND
P
T
Tstg
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to V
CC
+ 0.5
–0.5 to 7.0
–20
±50
±25
±50
785
500
–65 to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Conditions
Output: H or L
V
CC
: OFF
V
I
< 0
V
O
< 0 or V
O
> V
CC
V
O
= 0 to V
CC
SOP
TSSOP
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Supply voltage range
Input voltage range
Output voltage range
Output current
Symbol
V
CC
V
I
V
O
I
OH
Min
2.0
0
0
—
—
—
—
—
—
—
—
0
0
0
–40
Max
5.5
5.5
V
CC
–50
–2
–6
–12
50
2
6
12
200
100
20
85
Unit
V
V
V
µA
mA
Conditions
I
OL
µA
mA
Input transition rise or fall rate
∆t
/∆v
ns/V
H or L
V
CC
= 2.0 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 2.0 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
V
CC
= 2.3 to 2.7 V
V
CC
= 3.0 to 3.6 V
V
CC
= 4.5 to 5.5 V
Operating free-air temperature
Ta
°C
Note: Unused or floating inputs must be held high or low.
Rev.3.00 Jun. 28, 2004 page 3 of 10
HD74LV393A
Logic Diagram
D
D
D
D
CLK
CK
R
Q
CK
R
Q
CK
R
Q
CK
R
Q
CLR
QA
QB
QC
QD
Timing Diagram
CLK
CLR
QA
QB
QC
QD
Rev.3.00 Jun. 28, 2004 page 4 of 10
HD74LV393A
DC Electrical Characteristics
Ta = –40 to 85°C
Item
Input voltage
Symbol
V
IH
V
CC
(V)*
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
Min to Max
2.3
3.0
4.5
Min to Max
2.3
3.0
4.5
0 to 5.5
5.5
0
3.3
Min
1.5
V
CC
×
0.7
V
CC
×
0.7
V
CC
×
0.7
—
—
—
—
V
CC
– 0.1
2.0
2.48
3.8
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1.7
Max
—
—
—
—
0.5
V
CC
×
0.3
V
CC
×
0.3
V
CC
×
0.3
—
—
—
—
0.1
0.4
0.44
0.55
±1
20
5
—
Unit
V
Test Conditions
V
IL
Output voltage
V
OH
V
V
OL
V
Input current
Quiescent supply
current
Output leakage
current
Input capacitance
I
IN
I
CC
I
OFF
C
IN
µA
µA
µA
pF
I
OH
= –50
µA
I
OH
= –2 mA
I
OH
= –6 mA
I
OH
= –12 mA
I
OL
= 50
µA
I
OL
= 2 mA
I
OL
= 6 mA
I
OL
= 12 mA
V
IN
= 5.5 V or GND
V
IN
= V
CC
or GND, I
O
= 0
V
I
or V
O
= 0 V to 5.5 V
V
I
= V
CC
or GND
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Switching Characteristics
V
CC
= 2.5 ± 0.2 V
Ta = 25°C
Item
Maximum clock
frequency
Propagation
delay time
Symbol
fmax
t
PLH
/t
PHL
Min
50
30
—
—
—
—
—
—
—
—
—
—
6.0
5.0
5.0
Typ
90
60
11.8
15.1
13.4
16.7
14.9
18.2
16.2
19.5
10.8
14.2
—
—
—
Max
—
—
17.7
21.3
20.3
23.9
22.5
26.1
24.2
27.8
14.8
17.4
—
—
—
Ta = –40 to 85°C
Min
40
25
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
6.0
5.0
5.0
Max
—
—
20.5
24.5
23.5
27.5
26.0
30.0
28.0
32.0
17.0
20.0
—
—
—
Unit
MHz
ns
Test
Conditions
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
C
L
= 15 pF
C
L
= 50 pF
ns
ns
FROM
(Input)
TO
(Output)
CLK
Q
A
Q
B
Q
C
Q
D
t
PHL
Setup time
Pulse width
t
su
t
w
CLR
Q
n
CLR L before
CLK
↓
CLR H
CLK
H or L
Rev.3.00 Jun. 28, 2004 page 5 of 10
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