H8S/2345 Series
H8S/2345, H8S/2344, H8S/2343,
H8S/2341, H8S/2340
H8S/2345 F-ZTAT
Hardware Manual
TM
ADE-602-129B
Rev. 3.0
9/17/99
Hitachi, Ltd.
Cautions
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have received the latest product standards or specifications before final design, purchase or
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demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
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life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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Preface
The H8S/2345 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
On-chip memory consists of large-capacity ROM and RAM. With regard to on-chip ROM*
1
,
single power supply flash memory (F-ZTAT™*
2
), PROM (ZTAT™*
2
), and mask ROM versions
are available, providing a quick and flexible response to conditions from ramp-up through full-
scale volume production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), 8-bit timers, watchdog timer
(WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
Use of the H8S/2345 Series enables compact, high-performance systems to be implemented easily.
This manual describes the hardware of the H8S/2345 Series. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Notes: 1. The H8S/2345, H8S/2344, H8S/2343, and H8S/2341 have on-chip ROM.
The H8S/2340 does not have on-chip ROM.
2. F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.
ZTAT is a trademark of Hitachi, Ltd.
Revisions and Additions in this Edition
Page
5
Item
Table 1.1 Overview
(Operating modes) Note
5
Table 1.1 Overview
(Packages), (Product lineup) Notes
7
74
105
Figure 1.2 Pin Arrangement
3.3.7 Mode 7
Table 5.3 Correspondence between
Interrupt Sources and IPR Settings Note
Table 8.1 Port Functions (Port G)
11.2.3 Reset Control/Status Register
Bit 7 table
471
537 to
608
571
12.5 Usage Notes Switching from SCK
Pin Function to Port Pin Function
Section 17
17.8.1 Boot Mode
On-Chip RAM Area Divisions in Boot Mode
572
17.8.1 Boot Mode
Notes on Use of User Mode
573
17.8.1 Boot Mode
Notes on Use of User Mode
579
592
17.9.4 Erase-Verify Mode
Table 17.22 DC Characteristics in Writer
Mode
[Amendment]
Note 1 mode programming setup time t
MDS
(min)= 200 ns
[Amendment]
Cleared after the elapse of (ß)
µs
or more
[Amendments]
Values of the following items:
•
Output high-level voltage
•
Output low-Level voltage
•
Input leak current
•
V
CC
current
Amendment of TBD values
Revision
[Amendment]
Modes 2, 3, 6, and 7 are not available on
the ROMless version.
Amended in line with completion of TFP-
100G development
Amended in line with completion of TFP-
100G development
[Amendment]
Note: 1. Not used on ROMless version
[Amendment]
Reserved bits. Only 1 should be written to
these bits.
Amended: Functions amended in
accordance with notes 3 and 4
[Amendment]
Cleared by reading RSTCR when WOVF =
1, then writing 0 to WOVF
Added
Deleted Part denoted "Preliminary"
Amendment of TBD values
205
399
i
Page
605 to
607
608
Item
Figure 17.36 to Figure 17.38
Mode programming setup time
17.15 Notes when Converting the F–
ZTAT Application Software to the Mask-
ROM Versions
Table 18.2 Damping Resistance Value
Table 18.3 Crystal Resonator
Parameters
Table 18.4 External Clock Input
Conditions
19.2.1 Standby Control Register
(SBYCR)
Bits 6 to 4 (standby time when using
external clock)
19.6.3 Setting Oscillation Stabilization
Time after Clearing Software Standby
Mode
Using an External Clock
Revision
[Amendment] t
MDS
(min) = 200 ns
Added
611
612
614
Added 10 MHz added
Added 10 MHz added
[Amendment]
V
CC
= 2.7 to 5.5 V applies only to ZTAT,
mask ROM, and ROMless versions
[Amendment]
The 16-state standby time cannot be
used in the F-ZTAT version; a standby
time of 8192 states or longer should be
used.
[Amendment]
The 16-state standby time cannot be
used in the F-ZTAT version; a standby
time of 8192 states or longer should be
used.
[Amendment]
The operating temperature range for flash
memory programming/erase operations is
T
a
= 0 to +75°C (regular specifications),
T
a
= 0 to +85°C (wide-range
specifications).
[Amendments]
Values of the following items:
•
Current dissipation
•
Analog power supply current
•
Referencecurrent
•
TBD value in Note4
[Deletion]
Characteristics table for conditions V
CC
=
AV
CC
= 3.0 V to 3.6 V, Vref = 3.0 V to
AV
CC
, V
SS
= AV
SS
= 0 V
619
626
631
Table 20.1 Absolute Maximum Ratings
633
Table 20.2 DC Characteristics
ii