Integrated
Circuit
Systems, Inc.
ICS9250-10
Frequency Timing Generator for Pentium
II
Systems
General Description
The
ICS9250-10
is a single chip clock for Intel Pentium II.
It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9250-10
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Features
Generates the following system clocks:
- 3 CPU (2.5V) 66.6/100 MHz (up to 133MHz through
I
2
C selection)
- 9 SDRAM (3.3V) up to 133MHz
- 8 PCI (3.3 V) @33.3MHz
- 2 IOAPIC (2.5V) @16.67 or 33.3MHz
- 2 Hublink clocks (3.3 V) @ 66.6 MHz
- 2 USB (3.3V) @ 48 MHz ( Non spread spectrum)
- 1 REF (3.3V) @ 14.318 MHz
Supports spread spectrum modulation ,
down spread 0 to -0.5%
I
2
C support for power management
Efficient power management scheme through PD#
Uses external 14.138 MHz crystal
Block Diagram
Pin Configuration
56-Pin 300 mil SSOP
*60K ohm pull-up to VDD on indicated inputs.
Power Groups
VDD0, GND0 = REF & Crystal
VDD1, GND1 = 3V66 [1:0]
VDD2, GND2 = PCICLK[7:0]
VDD3, GND3 = PLL core
VDD4, GND4 = 48MHz [1:0]
VDD5, GND5 = SDRAM_F, SDRAM [7:0]
VDDL0, GNDL0 = CPUCLK [2:0]
VDDL1, GNDL1 = IOAPIC [1:0]
Pentium
II
is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
9250-10 Rev K 12/14/01
ICS9250-10
Pin Descriptions
PIN NUMBER
P I N NA M E
FREQ_APIC
REF0
3
4
5, 6, 14, 17, 23,
24, 35, 41, 47
8, 7
X1
X2
GND (0:5)
3V66 [1:0]
TYPE
IN
OUT
IN
OUT
PWR
OUT
PWR
OUT
OUT
IN
IN
IN
IN
OUT
OUT
PWR
OUT
PWR
OUT
DESCRIPTION
Latched input at Power On. this determines the IOAPIC frequency.
When a "0" is latched, IOAPIC Freq=16.67MHz
When "1" is latched, IOAPIC Freq=33.3MHz
This pin has a 60K internal pull-up.
3.3V, 14.318MHz reference clock output.
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Ground pins for 3.3V supply
3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B
3.3V power supply
3.3V PCI clock outputs, with Synchronous CPUCLKS
3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s f o r U S B
Function Select pins. Determines CPU frequency, all output
functionality. Please refer to Functionality table on page 3.
Data input for I
2
C serial input.
Clock input of I
2
C input
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
3.3V output running 100MHz. All SDRAM outputs can be turned
off through I
2
C
3.3V free running 100MHz SDRAM not affected by I
2
C
Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output. 66MHz or 100MHz depending on FS
(0:1) pins Refer page 3.
2.5V power suypply for CPU & IOAPIC
2.5V clock outputs running at 16.67MHz or 33.3MHz.
1
2, 9, 10, 21,
VDD (0:5)
22, 27, 33, 38, 44
20,19,18,16,
PCICLK[7:0]
15,13,12,11
25, 26
28, 29
30
31
32
48MHz (0:1)
FS (0:1)
SDATA
SCLK
PD#
36, 37, 39, 40, 42,
SDRAM [7:0]
43, 45, 46
34
56,48
49,50,52
51, 53
54, 55
SDRAM_F
GNDL [1:0]
CPUCLK [2:0]
VDDL (0:1)
IOAPIC [1:0]
2
ICS9250-10
Functionality Table
FS1
0
0
1
1
FS0
0
1
0
1
CPU
Hi-Z
TCLK/2
66 MHz
100 MHz
SDRAM
Hi-Z
TCLK/4
100 MHz
100 MHz
3V66
Hi-Z
TCLK/4
66 MHz
66 MHz
PCICLK
Hi-Z
TCLK/8
33 MHz
33MHz
48MHz
Hi-Z
TCLK/2
48 MHz
48 MHz
REF0
Hi-Z
TCLK
14.318MHz
14.318MHZ
IOAPIC
Hi-Z
TCLK/16
16.67MHz
16.67MHz
Notes
Tristate
Test Mode
Clock Enable Configuration
PD#
0
1
CPUCLK
LOW
ON
SDRAM
LOW
ON
IOAPIC
LOW
ON
66MHz
LOW
ON
PCICLK
LOW
ON
REF,
48MHz
LOW
ON
Osc
OFF
ON
VCOs
OFF
ON
Select Functions
FS1
0
0
1
1
FS0
0
1
0
1
Tristate
Test Mode
Active CPU = 66MHz
Active CPU = 100MHz
Notes
3
ICS9250-10
Power Down Waveform
Note
1.
After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2.
Power-up latency <3ms.
3.
Waveform shown for 100MHz
Maximum Allowed Current
810E
Condition
Powerdown Mode
(PWRDWN# = 0
Full Active 66MHz
SEL1, 0 = 10
Full Active 100MHz
SEL1, 0 = 11
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
All static inputs = Vddq3 or GND
10mA
70mA
100mA
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
All static inputs = Vddq3 or GND
10mA
280mA
280mA
4
ICS9250-10
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will
acknowledge
each byte
one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
ACK
Stop Bit
ACK
Byte 5
ACK
Byte 4
ACK
Byte 3
ACK
Byte 2
ACK
Byte 1
ACK
Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
