4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Mobile LPDDR2 SDRAM
MT42L256M16D1, MT42L128M32D1, MT42L256M32D2,
MT42L128M64D2, MT42L512M32D4, MT42L192M64D3,
MT42L256M64D4, MT42L384M32D3
Features
• Ultra low-voltage core and I/O power supplies
– V
DD2
= 1.14–1.30V
– V
DDCA
/V
DDQ
= 1.14–1.30V
– V
DD1
= 1.70–1.95V
• Clock frequency range
– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)
• Four-bit prefetch DDR architecture
• Eight internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on every CK edge
• Bidirectional/differential data strobe per byte of
data (DQS/DQS#)
• Programmable READ and WRITE latencies (RL/WL)
• Programmable burst lengths: 4, 8, or 16
• Per-bank refresh for concurrent operation
• On-chip temperature sensor to control self refresh
rate
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock stop capability
• RoHS-compliant, “green” packaging
Table 1: Key Timing Parameters
Speed Clock Rate Data Rate
Grade
(MHz)
(Mb/s/pin)
-18
-25
-3
533
400
333
1066
800
667
RL
8
6
5
WL
4
3
2
t
RCD/
t
RP
1
Options
Marking
Typical
Typical
Typical
• V
DD2
: 1.2V
L
• Configuration
– 32 Meg x 16 x 8 banks x 1 die
256M16
– 16 Meg x 32 x 8 banks x 1 die
128M32
– 16 Meg x 32 x 8 banks x 2 die
256M32
– 1 (16 Meg x 32 x 8 banks) + 2 (32
384M32
Meg x 16 x 8 banks)
– 32 Meg x 16 x 8 banks x 4 die
512M32
– 16 Meg x 32 x 8 banks x 2 die
128M64
– 16 Meg x 32 x 8 banks x 3 die
192M64
– 16 Meg x 32 x 8 banks x 4 die
256M64
• Device type
– LPDDR2-S4, 1 die in package
D1
– LPDDR2-S4, 2 die in package
D2
– LPDDR2-S4, 3 die in package
D3
– LPDDR2-S4, 4 die in package
D4
• FBGA “green” package
– 134-ball FBGA (10mm x
GU, GV
11.5mm)
– 168-ball FBGA (12mm x 12mm)
LF, LG
– 216-ball FBGA (12mm x 12mm) LH, LK, LL, LM,
LP
– 220-ball FBGA (14mm x 14mm)
LD, MP
– 240-ball FBGA (14mm x 14mm)
MC
– 253-ball FBGA (11mm x 11mm)
EU, EV
• Timing – cycle time
– 1.875ns @ RL = 8
-18
– 2.5ns @ RL = 6
-25
– 3.0ns @ RL = 5
-3
• Operating temperature range
– From –30°C to +85°C
WT
– From –40°C to +105°C
AT
• Revision
:A
Note:
1. For Fast
t
RCD/
t
RP, contact factory.
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Table 2: Single Channel S4 Configuration Addressing
Architecture
Die
configuration
CS0#
CS1#
Row addressing
Column
addressing
Number of die
Die per rank
CS0#
CS1#
Ranks per channel
1
Note:
CS0#
CS1#
256 Meg x 16
32 Meg x 16 x 8
banks
n/a
16K (A[13:0])
2K (A[10:0])
n/a
1
1
0
1
128 Meg x 32
16 Meg x 32 x 8
banks
n/a
16K (A[13:0])
1K (A[9:0])
n/a
1
1
0
1
256 Meg x 32
16 Meg x 32 x 8
banks
16 Meg x 32 x 8
banks
16K (A[13:0])
1K (A[9:0])
1K (A[9:0])
2
1
1
2
384 Meg x 32
16 Meg x 32 x 8
banks
32 Meg x 32 x 8
banks
16K (A[13:0])
1K (A[9:0])
2K (A[10:0])
3
1
2
2
512 Meg x 32
32 Meg x 16 x 8
banks
32 Meg x 16 x 8
banks
16K (A[13:0])
2K (A[10:0])
2K (A[10:0])
4
2
2
2
1. A channel is a complete LPDRAM interface, including command/address and data pins.
Table 3: Dual Channel S4 Configuration Addressing
Architecture
Die configuration
Row addressing
Column addressing
Number of die
Die per rank
CS0#
CS1#
Ranks per channel
1
Channel A
Channel B
Note:
CS0#
CS1#
128 Meg x 64
16 Meg x 32 x 8 banks
16K (A[13:0])
1K (A[9:0])
n/a
2
1
0
1
1
192 Meg x 64
16 Meg x 32 x 8 banks
16K (A[13:0])
1K (A[9:0])
1K (A[9:0])
3
1
1 = Channel A
0 = Channel B
2
1
256 Meg x 64
16 Meg x 32 x 8 banks
16K (A[13:0])
1K (A[9:0])
1K (A[9:0])
4
1
1
2
2
1. A channel is a complete LPDRAM interface, including command/address and data pins.
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Figure 1: 4Gb LPDDR2 Part Numbering
MT
42
L
128M32
D1
GU
-25
WT
:A
Micron Technology
Product Family
42 = Mobile LPDDR2 SDRAM
Design Revision
:A = First generation
Operating Temperature
WT = –30°C to +85°C
AT = –40°C to +105°C
Operating Voltage
L = 1.2V
Cycle Time
Configuration
256M16 = 256 Meg x 16
128M32 = 128 Meg x 32
256M32 = 256 Meg x 32
384M32 = 384 Meg x 32
512M32 = 512 Meg x 32
128M64 = 128 Meg x 64
192M64 = 192 Meg x 64
256M64 = 256 Meg x 64
-18 = 1.875ns,
t
CK RL = 8
-25 = 2.5ns,
t
CK RL = 6
-3 = 3.0ns,
t
CK RL = 5
Package Codes
GU, GV
LF, LG
LD, MP
MC
EU, EV
= 134-ball FBGA, 10mm x 11.5mm
= 168-ball FBGA, 12mm x 12mm
= 220-ball FBGA, 14mm x 14mm
= 240-ball FBGA, 14mm x 14mm
= 253-ball FBGA, 11mm x 11mm
LH, LK, LL, LM, LP = 216-ball FBGA, 12mm x 12mm
Addressing
D1 = LPDDR2, 1 die
D2 = LPDDR2, 2 die
D3 = LPDDR2, 3 die
D4 = LPDDR2, 4 die
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder.
Table 4: Package Codes and Descriptions
Package
Code
GU
GV
LF
LG
LH
LL
LM
LK
LP
MP
LD
MC
EU
EV
Notes:
Ball Count
134
134
168
168
216
216
216
216
216
220
220
240
253
253
# Ranks
1
2
1
2
1
1
2
2
2
1
2
1
1
2
# Channels
1
1
1
1
1 (Chan B only)
2
2
1 (Chan B only)
1 (Chan B only)
2
2
2
2
2
Size (mm)
10 x 11.5 x 0.7, 0.65 pitch
10 x 11.5 x 0.85, 0.65 pitch
12 x 12 x 0.75, 0.5 pitch
12 x 12 x 0.8, 0.5 pitch
12 x 12 x 0.65, 0.4 pitch
12 x 12 x 0.8, 0.4 pitch
12 x 12 x 1.0, 0.4 pitch
12 x 12 x 0.8, 0.4 pitch
12 x 12 x 0.82, 0.4 pitch
14 x 14 x 0.8, 0.5 pitch
14 x 14 x 1.0, 0.5 pitch
14 x 14 x 0.8, 0.5 pitch
11 x 11 x 0.9, 0.5 pitch
11 x 11 x 1.2, 0.5 pitch
Die per
Package
SDP
DDP
SDP
DDP
SDP
DDP
QDP
DDP
3DP
DDP
QDP
DDP
DDP
QDP
Solder Ball
Composition
LF35 (w/OSP)
LF35 (w/OSP)
SAC305
SAC305
SAC305
SAC305
SAC305
SAC305
SAC305
SAC305
SAC305
SAC305
LF35 (w/OSP)
LF35 (w/OSP)
1. SDP = single-die package, DDP = dual-die package, 3DP = triple-die package, QDP = quad-die package
2. Solder ball material: LF35 with Cu OSP ball pads (98.25% Sn, 1.2% Ag, 0.5% Cu, 0.05% Ni),
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Features
Contents
General Description ....................................................................................................................................... 12
General Notes ............................................................................................................................................ 12
I
DD
Specifications ........................................................................................................................................... 13
Package Block Diagrams ................................................................................................................................. 18
Package Dimensions ....................................................................................................................................... 24
Ball Assignments and Descriptions ................................................................................................................. 37
Functional Description ................................................................................................................................... 46
Power-Up ....................................................................................................................................................... 47
Initialization After RESET (Without Voltage Ramp) ...................................................................................... 49
Power-Off ....................................................................................................................................................... 49
Uncontrolled Power-Off .............................................................................................................................. 50
Mode Register Definition ................................................................................................................................ 50
Mode Register Assignments and Definitions ................................................................................................ 50
ACTIVATE Command ..................................................................................................................................... 61
8-Bank Device Operation ............................................................................................................................ 61
Read and Write Access Modes ......................................................................................................................... 62
Burst READ Command ................................................................................................................................... 62
READs Interrupted by a READ ..................................................................................................................... 69
Burst WRITE Command .................................................................................................................................. 69
WRITEs Interrupted by a WRITE ................................................................................................................. 72
BURST TERMINATE Command ...................................................................................................................... 72
Write Data Mask ............................................................................................................................................. 74
PRECHARGE Command ................................................................................................................................. 75
READ Burst Followed by PRECHARGE ......................................................................................................... 76
WRITE Burst Followed by PRECHARGE ....................................................................................................... 77
Auto Precharge ........................................................................................................................................... 78
READ Burst with Auto Precharge ................................................................................................................. 78
WRITE Burst with Auto Precharge ............................................................................................................... 79
REFRESH Command ...................................................................................................................................... 81
REFRESH Requirements ............................................................................................................................. 87
SELF REFRESH Operation ............................................................................................................................... 89
Partial-Array Self Refresh – Bank Masking .................................................................................................... 90
Partial-Array Self Refresh – Segment Masking .............................................................................................. 91
MODE REGISTER READ ................................................................................................................................. 92
Temperature Sensor ................................................................................................................................... 94
DQ Calibration ........................................................................................................................................... 96
MODE REGISTER WRITE Command ............................................................................................................... 98
MRW RESET Command .............................................................................................................................. 98
MRW ZQ Calibration Commands ................................................................................................................ 99
ZQ External Resistor Value, Tolerance, and Capacitive Loading .................................................................... 101
Power-Down ................................................................................................................................................. 101
Deep Power-Down ........................................................................................................................................ 108
Input Clock Frequency Changes and Stop Events ............................................................................................ 109
Input Clock Frequency Changes and Clock Stop with CKE LOW .................................................................. 109
Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 110
NO OPERATION Command ........................................................................................................................... 110
Simplified Bus Interface State Diagram ....................................................................................................... 110
Truth Tables .................................................................................................................................................. 112
Electrical Specifications ................................................................................................................................. 120
Absolute Maximum Ratings ....................................................................................................................... 120
PDF: 09005aef84427aab
4gb_mobile_lpddr2_s4_u80m.pdf - Rev. O 08/13 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
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