Hitachi Single-Chip Microcomputer
H8S/2128 Series
H8S/2127
HD6432127RW, HD6432127R
H8S/2126
HD6432126RW, HD6432126R
H8S/2124 Series
H8S/2122
HD6432122
H8S/2120
HD6432120
H8S/2128 F-ZTAT™
HD64F2128
Hardware Manual
ADE-602-114B
Rev. 3.0
03/26/01
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
The H8S/2128 Series and H8S/2124 Series comprise high-performance microcomputers with a
32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system
configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen
internal 16-bit general registers with a 32-bit configuration, and a concise and optimized
instruction set. The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes).
Programs based on the high-level language C can also be run efficiently.
Single-power-supply flash memory (F-ZTAT™*) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip peripheral functions include a 16-bit free-running timer module (FRT), 8-bit timer
module (TMR), watchdog timer module (WDT), two PWM timers (PWM and PWMX), a serial
communication interface (SCI), A/D converter (ADC), and I/O ports. An I
2
C bus interface (IIC)
can also be incorporated as an option.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
The H8S/2128 Series has all the above on-chip supporting functions, and can also be provided
with an IIC module as an options. The H8S/2124 Series comprises reduced-function versions, with
fewer TMR, and no PWM, IIC, or DTC modules.
Use of the H8S/2128 or H8S/2124 Series enables compact, high-performance systems to be
implemented easily. The various timer functions and their interconnectability (timer connection),
plus the interlinked operation of the I
2
C bus interface and data transfer controller (DTC), in
particular, make these devices ideal for use in PC monitors. In addition, the combination of F-
ZTAT
TM
and reduced-function versions is ideal for system applications in which on-chip program
memory is essential to meet performance requirements, product start-up times are short, and
program modifications may be necessary after end-product assembly.
This manual describes the hardware of the H8S/2128 Series and H8S/2124 Series. Refer to the
H8S/2600 Series and H8S/2000 Series Programming Manual
for a detailed description of the
instruction set.
Note: * F-ZTAT
TM
(Flexible-ZTAT) is a trademark of Hitachi, Ltd.
On-Chip Supporting Modules
Series
Product names
Bus controller (BSC)
Data transfer controller (DTC)
8-bit PWM timer (PWM)
14-bit PWM timer (PWMX)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Timer connection
Watchdog timer (WDT)
Serial communication interface (SCI)
I
2
C bus interface (IIC)
A/D converter
H8S/2128 Series
H8S/2128, 2127
Available (8 bits)
Available
×16
×2
×1
×4
Available
×2
×2
×2
(option)
H8S/2124 Series
H8S/2122, 2120
Available (8 bits)
—
—
—
×1
×3
—
×2
×2
—
×8
(analog inputs)
×8
(analog inputs)
×8
(expansion A/D inputs)
×8
(expansion A/D inputs)
Revisions and Additions in this Edition
Page
—
1
4, 5
24, 26
27 to
72
70, 71
76
78
81
89
145
180,
183
Item
Preface
On-Chip Supporting Modules
1.1 Overview
Table 1.1 Overview
Table 1.4 Pin Functions
2. CPU
2.10 Usage Notes
3.2.2 System Control Register (SYSCR)
3.2.4 Serial/Timer Control Register (STCR)
3.5 Memory Map in Each Operating Mode
Table 4.1 Exception Types and Priority
6.4.5 Wait Control
8.1 Over Viwe
Revisions (See Manual for Details)
Modification
Modification of on-chip ROM size
Modification of memory, products lineup
Modification of SCI, port 4, and port 5
Modification of TAS instruction
Addition of note on STM/LDM instructions
Addition
Modification of bit 6; IOS enable (IOSE)
description
Modification of bit 7 to 5 description
Addition of description: “Do not ... ”
Modification of description
Modification of Figure 6.7 Example of Wait
State Insertion Timing
Table 8.1 H8/2128 Series Port Functions
Modification of port 2 description
Table 8.2 H8/2124 Series Port Functions
Modification of port 2 description
219
231
249
265
267
269
270
271
Table 9.2 PWM Timer Module Registers
Table 10.2 Register Configuration
11.2.4 Output Compare Register AR and AF
(OCRAR, OCRAF)
11.3.5 Timing of Input Capture Flag (ICF) setting
Figure 11.16 Input Capture Mask Signal Clearing
Timing
Figure 11.18 FRC write-Clear Contention
Figure 11.19 FRC write-Increment Contention
Figure 11.20 Contention between OCR Write and
Compare-match (When automatic Addition
Function Is Not Used)
Figure 11.21 Contention between OCRAR/OCRA
write and Compare-match (When automatic
Addition Function Is Used)
12.2.6 Serial/Timer Control Register (STCR)
12.2.8 Timer Connection Register S (TCONRS)
12.2.11 Input Capture Register R, and F
(TICRR,TICRF)
[TMRX Additional Functions]
12.3.6 Input Capture Operation
12.4 Interrupt Sources
Addition of note 2
Addition of note 2
Modification
Modification of Figure 11.11 Setting of Input
Capture Flag (ICFA/B/C/D)
Modification
Modification
Modification
Modification
272
Modification
288
290
291
Modification
Modification
Addition of reference
299
301
Addition
Modification of table number
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
