CY7C64713
EZ-USB FX1™ USB Microcontroller
Full Speed USB Peripheral Controller
Features
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Integrated, industry standard 8051 with enhanced features:
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Single chip integrated USB transceiver, SIE, and enhanced
8051 microprocessor
Fit, form, and function upgradable to the FX2LP (CY7C68013A)
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Up to 48 MHz clock rate
Four clocks for each instruction cycle
Two USARTS
Three counters or timers
Expanded interrupt system
Two data pointers
Pin compatible
Object code compatible
Functionally compatible (FX1 functionality is a subset of the
FX2LP)
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3.3 V operation with 5 V tolerant inputs
Smart SIE
Vectored USB interrupts
Separate data buffers for the setup and DATA portions of a
CONTROL transfer
Integrated I
2
C controller, running at 100 or 400 KHz
48 MHz, 24 MHz, or 12 MHz 8051 operation
Four integrated FIFOs
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Draws no more than 65 mA in any mode, making the FX1
suitable for bus powered applications
Software: 8051 runs from internal RAM, which is:
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Downloaded using USB
Loaded from EEPROM
External memory device (128 pin configuration only)
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16 KB of on-chip code/data RAM
Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
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Brings glue and FIFOs inside for lower system cost
Automatic conversion to and from 16-bit buses
Master or slave operation
FIFOs can use externally supplied clock or asynchronous
strobes
Easy interface to ASIC and DSP ICs
Buffering options: double, triple, and quad
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Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
8- or 16-bit external data interface
Smart media standard ECC generation
GPIF
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Vectored for FIFO and GPIF Interrupts
Up to 40 general purpose IOs (GPIO)
Four package options:
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Allows direct connection to most parallel interfaces; 8- and
16-bit
Programmable waveform descriptors and configuration
registers to define waveforms
Supports multiple ready (RDY) inputs and Control (CTL)
outputs
128-pin TQFP
100-pin TQFP
56-pin SSOP
56-pin QFN Pb-free
Cypress Semiconductor Corporation
Document #: 38-08039 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 4, 2011
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CY7C64713
Logic Block Diagram
24 MHz
Ext. XTAL
High performance micro
using standard tools
with lower-power options
Address (16)
Data (8)
FX1
Address (16) / Data Bus (8)
VCC
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
Master
Additional IOs (24)
1.5k
connected for
enumeration
D+
USB
D–
Integrated
full speed XCVR
XCVR
CY
16 KB
RAM
Abundant I/O
including two USARTS
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
ADDR (9)
GPIF
ECC
RDY (6)
CTL (6)
Smart
USB
Engine
4 kB
FIFO
8/16
Up to 96 MBytes
burst rate
Enhanced USB core
Simplifies 8051 code
‘Soft Configuration’
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Document #: 38-08039 Rev. *I
Page 2 of 58
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CY7C64713
Contents
Functional Description ..................................................... 4
Applications ...................................................................... 4
Functional Overview ........................................................ 4
USB Signaling Speed .................................................. 4
8051 Microprocessor ................................................... 4
I
2
C Bus ........................................................................ 5
Buses .......................................................................... 5
USB Boot Methods ...................................................... 5
ReNumeration™ .......................................................... 5
Bus-powered Applications ........................................... 6
Interrupt System .......................................................... 6
Reset and Wakeup ...................................................... 7
Program/Data RAM ..................................................... 8
Endpoint RAM ........................................................... 11
External FIFO Interface ............................................. 11
GPIF .......................................................................... 12
ECC Generation ........................................................ 12
0.0.0.2 USB Uploads and Downloads ....................... 13
0.0.0.2 Autopointer Access ....................................... 13
0.0.0.2 I
2
C Controller ................................................. 13
Compatible with Previous Generation EZ-USB FX2 . 13
Pin Assignments ............................................................ 13
CY7C64713 Pin Definitions ............................................ 19
Register Summary .......................................................... 26
Absolute Maximum Ratings .......................................... 33
Operating Conditions ..................................................... 33
DC Characteristics ........................................................ 33
USB Transceiver ....................................................... 33
AC Electrical Characteristics ........................................ 34
USB Transceiver ....................................................... 34
PORTC Strobe Feature Timings ............................... 37
GPIF Synchronous Signals ....................................... 38
Slave FIFO Synchronous Read ................................. 39
Slave FIFO Asynchronous Read ............................... 40
Slave FIFO Synchronous Write ................................. 41
Slave FIFO Asynchronous Write ............................... 42
Slave FIFO Synchronous Packet End Strobe ........... 42
Slave FIFO Asynchronous Packet End Strobe ......... 44
Slave FIFO Output Enable ........................................ 44
Slave FIFO Address to Flags/Data ............................ 44
Slave FIFO Synchronous Address ............................ 45
Slave FIFO Asynchronous Address .......................... 45
Sequence Diagram .................................................... 46
Ordering Information ...................................................... 50
Ordering Code Definitions ......................................... 50
Package Diagrams .......................................................... 51
Quad Flat Package No Leads (QFN)
Package Design Notes ................................................... 54
Acronyms ........................................................................ 56
Document Conventions ................................................. 56
Units of Measure ....................................................... 56
Document History Page ................................................. 57
Sales, Solutions, and Legal Information ...................... 58
Worldwide Sales and Design Support ....................... 58
Products .................................................................... 58
PSoC Solutions ......................................................... 58
Document #: 38-08039 Rev. *I
Page 3 of 58
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CY7C64713
Functional Description
EZ-USB FX1™ (CY7C64713) is a full speed, highly integrated,
USB microcontroller. By integrating the USB transceiver, Serial
Interface Engine (SIE), enhanced 8051 microcontroller, and a
programmable peripheral interface in a single chip, Cypress has
created a very cost effective solution that provides superior
time-to-market advantages.
The EZ-USB FX1 is more economical, because it incorporates
the USB transceiver and provides a smaller footprint solution
than the USB SIE or external transceiver implementations. With
EZ-USB FX1, the Cypress Smart SIE handles most of the USB
protocol in hardware, freeing the embedded microcontroller for
application specific functions and decreasing the development
time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8 or 16-bit data bus) provide an easy and
glueless interface to popular interfaces such as ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
Four Pb-free packages are defined for the family: 56 SSOP, 56
QFN, 100 TQFP, and 128 TQFP.
8051 Microprocessor
The 8051 microprocessor embedded in the FX1 family has 256
bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
8051 Clock Frequency
FX1 has an on-chip oscillator circuit that uses an external 24
MHz (±100 ppm) crystal with the following characteristics:
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Parallel resonant
Fundamental mode
500
μW
drive level
12 pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY, and the internal counters
divide it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 is dynam-
ically changed by the 8051 through the CPUCS register.
The CLKOUT pin, which is three-stated and inverted using the
internal control bits, outputs the 50% duty cycle 8051 clock at the
selected 8051 clock frequency which is 48, 24, or 12 MHz.
USARTS
FX1 contains two standard 8051 USARTs, addressed by Special
Function Register (SFR) bits. The USART interface pins are
available on separate I/O pins, and are not multiplexed with port
pins.
UART0 and UART1 can operate using an internal clock at 230
KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48, 24, 12 MHz) such that
it always presents the correct frequency for 230-KBaud
operation.
[1]
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX1 functions. These SFR additions are shown
in
Table 1
on page 5. Bold type indicates non-standard,
enhanced 8051 registers. The two SFR rows that end with ‘0’ and
‘8’ contain bit addressable registers. The four I/O ports A–D use
the SFR addresses used in the standard 8051 for ports 0–3,
which are not implemented in the FX1. Because of the faster and
more efficient SFR addressing, the FX1 I/O ports are not addres-
sable in the external RAM space (using the MOVX instruction).
Applications
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DSL modems
ATA interface
Memory card readers
Legacy conversion devices
Home PNA
Wireless LAN
MP3 players
Networking
The
Reference Designs
section of the cypress website provides
additional tools for typical USB applications. Each reference
design comes complete with firmware source and object code,
schematics,
and
documentation.
Please
visit
http://www.cypress.com
for more information.
Functional Overview
USB Signaling Speed
FX1 operates at one of the three rates defined in the USB Speci-
fication Revision 2.0, dated April 27, 2000:
Full speed, with a signaling bit rate of 12 Mbps.
FX1 does not support the low speed signaling mode of 1.5 Mbps
or the high speed mode of 480 Mbps.
Notes
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a ‘1’ for UART0 and UART1, respectively.
2. The I
2
C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Document #: 38-08039 Rev. *I
Page 4 of 58
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CY7C64713
Figure 1. Crystal Configuration
C1
12 pF
24 MHz
C2
12 pF
12-pF capacitor values assumes
a trace capacitance of 3 pF per
side on a four layer FR4 PCA
20 × PLL
Table 1. Special Function Registers
x
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8x
IOA
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
SCON0
SBUF0
AUTOPTRH1
AUTOPTRL1
reserved
AUTOPTRH2
AUTOPTRL2
reserved
AUTOPTRSETUP
EP2468STAT
EP24FIFOFLGS
EP68FIFOFLGS
GPIFSGLDATH
GPIFSGLDATLX
GPIFSGLDATLNOX
VID/PID/DID (0x04B4, 0x6473, 0xAxxx where xxx=Chip
revision).
[2]
Table 2. Default ID Values for FX1
Default VID/PID/DID
Vendor ID 0x04B4 Cypress Semiconductor
Product ID 0x6473 EZ-USB FX1
Device
release
0xAnnn Depends on chip revision (nnn = chip
revision where first silicon = 001)
EP01STAT
GPIFTRIG
RCAP2L
RCAP2H
TL2
TH2
IE
IP
T2CON
EICON
EIE
EIP
9x
IOB
EXIF
MPAGE
Ax
IOC
INT2CLR
INT4CLR
Bx
IOD
IOE
OEA
OEB
OEC
OED
OEE
Cx
SCON1
SBUF1
Dx
PSW
Ex
ACC
Fx
B
I
2
C Bus
FX1 supports the I
2
C bus as a master only at 100/400 KHz. SCL
and SDA pins have open drain outputs and hysteresis inputs.
These signals must be pulled up to 3.3 V, even if no I
2
C device
is connected.
Buses
All packages: 8 or 16-bit ‘FIFO’ bidirectional data bus, multi-
plexed on I/O ports B and D. 128 pin package: adds 16-bit output
only 8051 address bus, 8-bit bidirectional data bus.
USB Boot Methods
During the power up sequence, internal logic checks the I
2
C port
for the connection of an EEPROM whose first byte is either 0xC0
or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
in place of the internally stored values (0xC0). Alternatively, it
boot-loads the EEPROM contents into an internal RAM (0xC2).
If no EEPROM is detected, FX1 enumerates using internally
stored descriptors. The default ID values for FX1 are
ReNumeration™
Because the FX1’s configuration is soft, one chip can take on the
identities of multiple distinct USB devices.
When first plugged into the USB, the FX1 enumerates automat-
ically and downloads firmware and the USB descriptor tables
over the USB cable. Next, the FX1 enumerates again, this time
as a device defined by the downloaded information. This
patented two step process, called ReNumeration, happens
instantly when the device is plugged in, with no indication that
the initial download step has occurred.
Document #: 38-08039 Rev. *I
Page 5 of 58
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