6. Configuring APEX II
Devices
CF51004-2.1
Introduction
APEX
TM
II devices can be configured using one of four configuration
schemes. All configuration schemes use either a microprocessor or
configuration device.
APEX II devices can be configured using the passive serial (PS), fast
passive parallel (FPP), passive parallel asynchronous (PPA), and Joint
Test Action Group (JTAG) configuration schemes. The configuration
scheme used is selected by driving the APEX II device
MSEL1
and
MSEL0
pins either high or low as shown in
Table 6–1.
If your application only
requires a single configuration mode, the
MSEL
pins can be connected to
V
CC
(V
CCIO
of the I/O bank where the
MSEL
pin resides) or to ground. If
your application requires more than one configuration mode, you can
switch the
MSEL
pins after the FPGA is configured successfully. Toggling
these pins during user-mode does not affect the device operation;
however, the
MSEL
pins must be valid before a reconfiguration is
initiated.
Table 6–1. APEX II Configuration Schemes
MSEL1
0
1
1
(1)
Notes to
Table 6–1:
(1)
Do not leave the
MSEL
pins floating; connect them to a low- or high-logic level.
These pins support the non-JTAG configuration scheme used in production. If
only JTAG configuration is used, you should connect the
MSEL
pins to ground.
JTAG-based configuration takes precedence over other configuration schemes,
which means
MSEL
pin settings are ignored.
MSEL0
0
0
1
(1)
Configuration Scheme
PS
FPP
PPA
JTAG Based
(2)
(2)
Altera Corporation
August 2005
6–1
Passive Serial Configuration
Table 6–2
shows the approximate configuration file sizes for APEX II
devices.
Table 6–2. APEX II Raw Binary File (.rbf) Sizes
Device
EP2A15
EP2A25
EP2A40
EP2A70
Data Size (Bits)
4,358,512
6,275,200
9,640,528
17,417,088
Data Size (Bytes)
544,814
784,400
1,208,320
2,177,136
Use the data in
Table 6–2
only to estimate the file size before design
compilation. Different configuration file formats, such as a Hexidecimal
(.hex) or Tabular Text File (.ttf) format, will have different file sizes.
However, for any specific version of the Quartus
®
II or MAX+PLUS
®
II
software, all designs targeted for the same device will have the same
configuration file size.
The following chapter describes in detail how to configure APEX II
devices using the supported configuration schemes. The last section
describes the device configuration pins available. In this chapter, the
generic term device(s) or FPGA(s) will include all APEX II devices.
f
For more information on setting device configuration options or creating
configuration files, refer to
Software Settings,
chapter 6 and 7 n volume 2
of the
Configuration Handbook.
You can perform APEX II PS configuration using an Altera configuration
device, an intelligent host (e.g., a microprocessor or Altera
®
MAX
®
device), or a download cable.
Passive Serial
Configuration
PS Configuration Using a Configuration Device
You can use an Altera configuration device, such as an enhanced
configuration device, EPC2, or EPC1 device, to configure APEX II devices
using a serial configuration bitstream. Configuration data is stored in the
configuration device.
Figure 6–1
shows the configuration interface
connections between the APEX II device and a configuration device.
1
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the FPGA.
6–2
Configuration Handbook, Volume 1
Altera Corporation
August 2005
Configuring APEX II Devices
f
For more information on the enhanced configuration device and flash
interface pins (e.g.,
PGM[2..0], EXCLK, PORSEL, A[20..0],
and
DQ[15..0]),
refer to the
Enhanced Configuration Devices (EPC4, EPC8 &
EPC16) Data Sheet
in the
Configuration Handbook.
Figure 6–1. Single Device PS Configuration Using an Enhanced Configuration
Device
VCC
(1)
VCC
(1)
APEX II Device
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
MSEL1
GND
nCEO
nCE
1 kΩ
(3)
1 kΩ
(3)
Enhanced
Configuration
Device
DCLK
DATA
OE
(3)
nCS
(3)
nINIT_CONF
(2)
N.C.
GND
Notes to
Figure 6–1:
(1)
(2)
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The
nINIT_CONF
pin (available on enhanced configuration devices and EPC2
devices only) has an internal pull-up resistor that is always active, meaning an
external pull-up resistor is not required on the
nINIT_CONF/nCONFIG
line. The
nINIT_CONF
pin does not need to be connected if its functionality is not used. If
nINIT_CONF
is not used or not available (e.g., on EPC1 devices),
nCONFIG
must
be pulled to V
CC
either directly or through a resistor.
The enhanced configuration devices’ and EPC2 devices’
OE
and
nCS
pins have
internal programmable pull-up resistors. If internal pull-up resistors are used,
external pull-up resistors should not be used on these pins. The internal pull-up
resistors are used by default in the Quartus II software. To turn off the internal pull-
up resistors, check the
Disable nCS and OE pull-ups on configuration device
option
when generating programming files.
(3)
f
The value of the internal pull-up resistors on the enhanced configuration
devices and EPC2 devices can be found in the Operating Conditions
table of the Enhanced Configuration Devices (EPC4, EPC8, & EPC16)
Data Sheet or the Configuration Devices for SRAM-based LUT Devices
Data Sheet.
When using enhanced configuration devices or EPC2 devices,
nCONFIG
of the FPGA can be connected to
nINIT_CONF,
which allows the
INIT_CONF
JTAG instruction to initiate FPGA configuration. The
nINIT_CONF
pin does not need to be connected if its functionality is not
used. If
nINIT_CONF
is not used or not available (e.g., on EPC1 devices),
nCONFIG
must be pulled to V
CC
either directly or through a resistor. An
Altera Corporation
August 2005
6–3
Configuration Handbook, Volume 1
Passive Serial Configuration
internal pull-up on the
nINIT_CONF
pin is always active in enhanced
configuration devices and EPC2 devices, which means an external pull-
up resistor is not required if
nCONFIG
is tied to
nINIT_CONF.
Upon power-up, the APEX II device goes through a Power-On Reset
(POR) for approximately 5
μs.
During POR, the device resets and holds
nSTATUS
low, and tri-states all user I/O pins.
The
configuration device
also goes through a POR delay to allow the power supply to stabilize. The
POR time for EPC2, EPC1, and EPC1441 devices is 200 ms (maximum),
and for enhanced configuration devices, the POR time can be set to either
100 ms or 2 ms, depending on its
PORSEL
pin setting. If the
PORSEL
pin
is connected to GND, the POR delay is 100 ms. During this time, the
configuration device drives its
OE
pin low. This low signal delays
configuration because the
OE
pin is connected to the target device’s
nSTATUS
pin. When both devices complete POR, they release their open-
drain
OE
or
nSTATUS
pin, which is then pulled high by a pull-up resistor.
Once the FPGA successfully exits POR, all user I/O pins are tri-stated.
APEX II devices have weak pull-up resistors on the user I/O pins which
are on before and during configuration.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Operating Conditions table
of the
APEX II Programmable Logic Device Family Data Sheet.
When the power supplies have reached the appropriate operating
voltages, the target FPGA senses the low-to-high transition on
nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization. While
nCONFIG
or
nSTATUS
are low, the device is in reset. The beginning of configuration
can be delayed by holding the
nCONFIG
or
nSTATUS
pin low.
1
VCCINT
and
VCCIO
pins on the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels to begin the configuration process.
When
nCONFIG
goes high, the device comes out of reset and releases the
nSTATUS
pin, which is pulled high by a pull-up resistor. Enhanced
configuration and EPC2 devices have an optional internal pull-up on the
OE
pin. This option is available in the Quartus II software from the
General
tab of the
Device & Pin Options
dialog box. If this internal pull-
up resistor is not used, an external 1-kΩ pull-up resistor on the
OE/nSTATUS
line is required. Once
nSTATUS
is released, the FPGA is
ready to receive configuration data and the configuration stage begins.
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Configuration Handbook, Volume 1
Altera Corporation
August 2005
Configuring APEX II Devices
When
nSTATUS
is pulled high,
OE
of the configuration device also goes
high and the configuration device clocks data out serially to the FPGA
using its internal oscillator. The APEX II device receives configuration
data on its
DATA0
pin and the clock is received on the
DCLK
pin. Data is
latched into the FPGA on the rising edge of
DCLK.
After the FPGA has received all configuration data successfully, it releases
the open-drain
CONF_DONE
pin, which is pulled high by a pull-up
resistor. Since
CONF_DONE
is tied to the configuration device’s
nCS
pin,
the configuration device is disabled when
CONF_DONE
goes high.
Enhanced configuration and EPC2 devices have an optional internal pull-
up resistor on the
nCS
pin. This option is available in the Quartus II
software from the
General
tab of the
Device & Pin Options
dialog box.
If this internal pull-up is not used, an external 1-kΩ pull-up resistor on the
nCS/CONF_DONE
line is required. A low-to-high transition on
CONF_DONE
indicates configuration is complete and initialization of the
device can begin.
In APEX II devices, the initialization clock source is either the APEX II
internal oscillator (typically 10 MHz) or the optional
CLKUSR
pin. By
default, the internal oscillator is the clock source for initialization. If the
internal oscillator is used, the APEX II device will supply itself with
enough clock cycles for proper initialization. You also have the flexibility
to synchronize initialization of multiple devices by using the
CLKUSR
option. You can turn on the
Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the
General
tab of the
Device &
Pin Options
dialog box. Supplying a clock on
CLKUSR
will not affect the
configuration process. After all configuration data is accepted and
CONF_DONE
goes high, APEX II devices require 40 clock cycles to
properly initialize.
Altera Corporation
August 2005
6–5
Configuration Handbook, Volume 1
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