GS832118/32/36E-250/225/200/166/150/133
165-Bump FP-BGA
Commercial Temp
Industrial Temp
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump FP-BGA package
• RoHS-compliant 165-bump BGA package available
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
250 MHz–133 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Functional Description
Applications
The GS832118/32/36E is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Re
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for
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Ne
w
Parameter Synopsis
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
-250 -225 -200 -166 -150 -133 Unit
2.5 2.7 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
285
350
6.5
6.5
205
235
265
320
7.0
7.0
195
225
245
295
7.5
7.5
185
210
220
260
8.0
8.0
175
200
210
240
8.5
8.5
165
190
185
215
8.5
8.5
155
175
mA
mA
ns
ns
mA
mA
No
t
Pipeline
3-1-1-1
Flow
Through
2-1-1-1
Rev: 1.05a 1/2012
1/32
De
sig
n—
Di
sco
nt
inu
ed
Pr
od
u
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS832118/32/36E is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832118/32/36E operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuits and are 3.3 V and 2.5 V compatible.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2003, GSI Technology
GS832118/32/36E-250/225/200/166/150/133
GS832118/32/36E 165-Bump BGA Pin Description
Symbol
A
0
, A
1
A
DQ
A
DQ
B
DQ
C
DQ
D
B
A
, B
B
, B
C
, B
D
NC
CK
BW
GW
E
1
E
3
E
2
G
ADV
ADSC, ADSP
ZZ
FT
LBO
TMS
TDI
TDO
TCK
MCL
V
DD
V
SS
V
DDQ
Type
I
I
I/O
I
—
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
—
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Byte Write Enable for DQ
A
, DQ
B
, DQ
C
, DQ
D
I/Os; active low
No Connect
Clock Input Signal; active high
Byte Write—Writes all enabled bytes; active low
Chip Enable; active low
Chip Enable; active low
Global Write Enable—Writes all bytes; active low
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect Low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.05a 1/2012
No
t
Re
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ed
for
Ne
w
5/32
De
sig
Burst address counter advance enable; active l0w
n—
Di
sco
nt
inu
ed
Pr
od
u
Data Input and Output pins
Chip Enable; active high
Output Enable; active low
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ct
© 2003, GSI Technology
Address Inputs
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