ADVANCED INFORMATION
MX25L6436F
MX25L6436F
3V, 64M-BIT [x 1/x 2/x 4]
CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
Key Features
• Special Block Protection Levels
• Multi I/O Support - Single I/O, Dual I/O and Quad I/O
• Hold Feature
• Program Suspend/Resume & Erase Suspend/Resume
P/N: PM2305
1
REV. 0.00, OCT. 22, 2015
ADVANCED INFORMATION
MX25L6436F
Contents
1. FEATURES ........................................................................................................................................................ 4
2. GENERAL DESCRIPTION ............................................................................................................................... 5
3. PIN CONFIGURATION ...................................................................................................................................... 6
4. PIN DESCRIPTION ............................................................................................................................................ 6
5. BLOCK DIAGRAM............................................................................................................................................. 7
6. DATA PROTECTION.......................................................................................................................................... 8
Table 1. Protected Area Sizes ................................................................................................................9
Table 2. 8K-bit Secured OTP Definition
...............................................................................................10
7. MEMORY ORGANIZATION ..............................................................................................................................11
Table 3. Memory Organization
............................................................................................................. 11
8. DEVICE OPERATION ...................................................................................................................................... 12
9. HOLD FEATURE.............................................................................................................................................. 13
10. COMMAND DESCRIPTION ........................................................................................................................... 14
Table 4. Command Sets
.......................................................................................................................14
10-1. Write Enable (WREN)
..........................................................................................................................17
10-2. Write Disable (WRDI)
...........................................................................................................................18
10-3. Read Identification (RDID)
...................................................................................................................19
10-4. Read Status Register (RDSR)
.............................................................................................................20
10-5. Read Configuration Register (RDCR)
..................................................................................................21
10-6. Write Status Register (WRSR)
.............................................................................................................24
Table 5. Protection Modes
....................................................................................................................25
10-7. Read Data Bytes (READ)
....................................................................................................................27
10-8. Read Data Bytes at Higher Speed (FAST_READ)
..............................................................................28
10-9. Dual Read Mode (DREAD)
..................................................................................................................29
10-10. 2 x I/O Read Mode (2READ)
...............................................................................................................30
10-11. Quad Read Mode (QREAD)
................................................................................................................31
10-12. 4 x I/O Read Mode (4READ)
...............................................................................................................32
10-13. Performance Enhance Mode
...............................................................................................................34
10-14. Burst Read
...........................................................................................................................................35
10-15. Sector Erase (SE)
................................................................................................................................36
10-16. Block Erase (BE)
.................................................................................................................................37
10-17. Block Erase (BE32K)
...........................................................................................................................38
10-18. Chip Erase (CE)
...................................................................................................................................39
10-19. Page Program (PP)
.............................................................................................................................40
10-20. 4 x I/O Page Program (4PP)
................................................................................................................41
10-21. Deep Power-down (DP)
.......................................................................................................................44
10-22. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
.......................................45
10-23. Read Electronic Manufacturer ID & Device ID (REMS)
.......................................................................47
Table 6. ID Definitions
.........................................................................................................................48
10-24. Enter Secured OTP (ENSO)
................................................................................................................48
10-25. Exit Secured OTP (EXSO)
...................................................................................................................48
10-26. Read Security Register (RDSCUR)
.....................................................................................................49
Table 7. Security Register Definition
....................................................................................................50
P/N: PM2305
REV. 0.00, OCT. 22, 2015
2
ADVANCED INFORMATION
MX25L6436F
Write Security Register (WRSCUR)
.....................................................................................................51
Write Protection Selection (WPSEL)
....................................................................................................52
Advanced Sector Protection
................................................................................................................54
Solid Protection Bits
.............................................................................................................................55
Program Suspend and Erase Suspend
...............................................................................................59
Table 8. Readable Area of Memory While a Program or Erase Operation is Suspended
....................59
Table 9. Acceptable Commands During Program/Erase Suspend after tPSL/tESL
.............................60
Table 10. Acceptable Commands During Suspend (tPSL/tESL not required)
......................................60
10-32. Program Resume and Erase Resume
.................................................................................................61
10-33. No Operation (NOP)
............................................................................................................................62
10-34. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
...............................................................62
10-35. Read SFDP Mode (RDSFDP)
..............................................................................................................63
Table 11. Signature and Parameter Identification Data Values
...........................................................64
Table 12. Parameter Table (0): JEDEC Flash Parameter Tables
.........................................................65
Table 13. Parameter Table (1): Macronix Flash Parameter Tables
......................................................67
11. POWER-ON STATE ....................................................................................................................................... 69
12. Electrical Specifications
.............................................................................................................................. 70
12-1. Absolute Maximum Ratings
.................................................................................................................70
12-2. Capacitance TA = 25°C, f = 1.0 MHz
...................................................................................................70
Table 14. DC Characteristics
................................................................................................................72
Table 15. AC Characteristics
................................................................................................................73
13. TIMING ANALYSIS ........................................................................................................................................ 75
14. OPERATING CONDITIONS ........................................................................................................................... 77
Table 16. Power-Up/Down Voltage and Timing
....................................................................................79
14-1. Initial Delivery State
.............................................................................................................................79
15. ERASE AND PROGRAMMING PERFORMANCE ........................................................................................ 80
16. DATA RETENTION ........................................................................................................................................ 80
17. LATCH-UP CHARACTERISTICS .................................................................................................................. 80
18. ORDERING INFORMATION .......................................................................................................................... 81
19. PART NAME DESCRIPTION ......................................................................................................................... 82
20. PACKAGE INFORMATION ............................................................................................................................ 83
20-1. 8-pin SOP (200mil)
..............................................................................................................................83
10-27.
10-28.
10-29.
10-30.
10-31.
P/N: PM2305
3
REV. 0.00, OCT. 22, 2015
ADVANCED INFORMATION
MX25L6436F
64M-BIT [x 1 / x 2 / x 4] CMOS MXSMIO
®
(SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
• Supports Serial Peripheral Interface -- Mode 0
and Mode 3
•
67,108,864 x 1 bit structure or 33,554,432 x 2
bits (two I/O read mode) structure or 16,777,216
x 4 bits (four I/O mode) structure
• 2048 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.65 to 3.6 volt for read, erase, and program
operations
• Latch-up protected to 100mA from -1V to Vcc
+1V
PERFORMANCE
• High Performance
VCC = 2.65~3.6V
- Normal read
- 50MHz
- Fast read
- FAST_READ, DREAD, QREAD: 133MHz
with 8 dummy cycles
- 2READ: 80MHz with 4 dummy cycle,
133MHz with 8 dummy cycle
- 4READ: 80MHz with 6 dummy cycle,
133MHz with 10 dummy cycle
- Configurable dummy cycle number for
2READ and 4READ operation
- 8/16/32/64 byte Wrap-Around Burst Read
Mode
• Low Power Consumption
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
•
Input Data Format
-
1-byte Command code
•
Advanced Security Features
- Special Block lock protection
The BP0-BP3 and T/B status bits define the size of
the area to be protected against program and erase
instructions
•
Additional 8K-bit bit security OTP
-
Features unique identifier
-
Factory locked identifiable, and customer lockable
•
Auto Erase and Auto Program Algorithms
-
Automatically erases and verifies data at selected
sector
-
Automatically programs and verifies data at selected
page by an internal algorithm that automatically
times the program pulse width (Any page to be pro-
grammed should have page in the erased state first.)
•
Status Register Feature
•
Command Reset
•
Program/Erase Suspend
•
Program/Erase Resume
•
Electronic Identification
-
JEDEC 1-byte Manufacturer ID and 2-byte Device ID
- RES command for 1-byte Device ID
•
Support Serial Flash Discoverable Parameters (SFDP)
mode
HARDWARE FEATURES
•
SCLK Input
• SI/SIO0
-
Serial Data Input or Serial Data Input/Output for 2 x I/
O mode or Serial Data Input/Output for 4 x I/O mode
• SO/SIO1
-
Serial Data Output or Serial Data Input/Output for 2 x
I/O mode or Serial Data Input/Output for 4 x I/O mode
• WP#/SIO2
-
Hardware write protection or serial data Input/Output
for 4 x I/O mode
• HOLD#/SIO3
-
To pause the device without deselecting the device or
serial data Input/Output for 4 x I/O mode
• PACKAGE
-
8-pin SOP (200mil)
-
All devices are RoHS Compliant and Halogen-free
-
Serial clock input
P/N: PM2305
4
REV. 0.00, OCT. 22, 2015
ADVANCED INFORMATION
MX25L6436F
2. GENERAL DESCRIPTION
MX25L6436F is 64Mb bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is in
four I/O mode, the structure becomes 16,777,216 bits x 4. When it is in two I/O mode, the structure becomes
33,554,432 bits x 2. MX25L6436F feature a serial peripheral interface and software protocol allowing operation
on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data
input (SI), and a serial data output (SO).
Serial
access to the device is enabled by CS# input.
MX25L6436F, MXSMIO
®
(Serial Multi I/O) flash memory, provides sequential read operation on the whole chip
and multi-I/O features.
When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin, SIO2 pin
and SIO3 pin for address/dummy bits input and data Input/Output.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis. Erase command is executed on 4K-byte sector, 32K-byte/64K-byte block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status
read command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The MX25L6436F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM2305
5
REV. 0.00, OCT. 22, 2015
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