SM572284578E83RTN
December 1, 2003
Orderable Part Numbers
Module Part Number
SM572284578E83RTN
Description
128Mx72 (1GB), SDRAM, 168-pin DIMM, Registered, 128Mx4 Based
(Stacked- two 64Mx4), CL = 4.0 (Device = 3.0), PC133, 27.98mm.
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SM572284578E83RTN
December 1, 2003
Revision History
• December 1, 2003
Datasheet released.
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SM572284578E83RTN
December 1, 2003
1GByte (128Mx72) SDRAM Module - 128Mx4 based (Stacked - two 64Mx4)
168-pin DIMM, Registered
Features
•
•
•
•
•
•
•
Standard
Configuration
Cycle Time
CAS# Latency
Burst Length
Burst Type
No. of Internal
Banks per SDRAM
:
:
:
:
:
:
:
PC133
ECC
7.5ns
4.0 (Device = 3.0)
1, 2, 4, 8 or Page
Linear/Interleave
4
•
•
•
•
•
•
•
Operating Voltage :
3.3V
Refresh
:
8K/64ms
Device Physicals
:
Stacked
Lead Finish
:
Gold
Length x Height
:
133.35mm x 27.98mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Vertical
:
AMP-390074-6
168-pin SDRAM DIMM Pin List
Pin Pin
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
Pin Pin
No. Name
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB1
V
SS
CB4
CB5
V
CC
WE#
DQMB0
DQMB1
CS0#
NC
V
SS
A0
A2
A4
A6
A8
A10/AP*
BA1
V
CC
V
CC
CK0
Pin Pin
No. Name
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
V
SS
NC
CS2#
DQMB2
DQMB3
NC
V
CC
CB12
CB13
CB8
CB9
V
SS
DQ16
DQ17
DQ18
DQ19
V
CC
DQ20
NC
NC
CKE1
Pin Pin
No. Name
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
CK2
NC
WP
SDA
SCL
V
CC
Pin Pin
No. Name
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
Pin Pin
No. Name
106 CB3
107 V
SS
108 CB6
109 CB7
110 V
CC
111 CAS#
112 DQMB4
113 DQMB5
114 CS1#
115 RAS#
116 V
SS
117 A1
118 A3
119 A5
120 A7
121 A9
122 BA0
123 A11
124 V
CC
125 CK1
126 A12
Pin Pin
No. Name
127 V
SS
128 CKE0
129 CS3#
130 DQMB6
131 DQMB7
132 NC
133 V
CC
134 CB14
135 CB15
136 CB10
137 CB11
138 V
SS
139 DQ48
140 DQ49
141 DQ50
142 DQ51
143 V
CC
144 DQ52
145 NC
146 NC
147 REGE
Pin Pin
No. Name
148 V
SS
149 DQ53
150 DQ54
151 DQ55
152 V
SS
153 DQ56
154 DQ57
155 DQ58
156 DQ59
157 V
CC
158 DQ60
159 DQ61
160 DQ62
161 DQ63
162 V
SS
163 CK3
164 NC
165 SA0
166 SA1
167 SA2
168 V
CC
100 DQ44
101 DQ45
102 V
CC
103 DQ46
104 DQ47
105 CB2
( All specifications of this device are subject to change without notice.)
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SM572284578E83RTN
December 1, 2003
Pin Description Table
Symbol
CK0~CK3
CKE0, CKE1
CS0#, CS1#,
CS2#, CS3#
RAS#, CAS#,
WE#
BA0, BA1
A0 ~ A9,
A10/AP,
A11, A12
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Polarity
Positive
Edge
Active High
Active Low
Active Low
-
-
Function
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their asso-
ciated clock.
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deacti-
vating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the oper-
ations to be executed by the SDRAM.
Selects which of the four internal SDRAM banks is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA9,
CA11) when sampled at the rising clock edge. In addition to the column address, A10/AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, auto-
precharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control
which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state
of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
Data and Check Bit Input/Output pins.
Data strobe for input and output data.
DQ0~DQ63
CB0~CB15
DQMB0~
DQMB7
REGE
SSTL
SSTL
-
Negative &
Positive
Edge
Active High
LVTTL
The Register Enable pin is used to permit the DIMM to operate in Buffered mode (inputs re-
driven asynchronously) or Registered mode (signals re-driven to SDRAMs when clock rises,
and held valid until next rising clock).
These signals are tied on the system to either V
SS
or V
CC
to configure the serial SPD.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must
be connected on the system board from the SDA bus line to V
CC
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected on the system board from the SCL bus line to V
CC
to act as a pullup.
Write protection.
Power and ground for the SDRAM input buffers and core logic.
No Connect
SA0~SA2
SDA
SCL
WP
V
CC,
V
SS
NC
LVTTL
LVTTL
LVTTL
LVTTL
Supply
Supply
-
-
-
-
-
-
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SM572284578E83RTN
December 1, 2003
CKE0
CKE1
CS0#
CS1#
DQMB0
DQMB S# CKE
DQ0
DQ1
DQ2
DQ3
DQMB0
DQMB S# CKE
DQ4
DQ5
DQ6
DQ7
DQMB1
DQMB S# CKE
DQ8
DQ9
DQ10
DQ11
DQMB1
DQMB S# CKE
DQ12
DQ13
DQ14
DQ15
DQMB1
DQMB S# CKE
CB0
CB1
CB2
CB3
DQMB2
DQMB S# CKE
DQ16
DQ17
DQ18
DQ19
DQMB2
DQMB S# CKE
DQ20
DQ21
DQ22
DQ23
DQMB3
DQMB S# CKE
DQ24
DQ25
DQ26
DQ27
DQMB3
DQMB S# CKE
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
CS2#
CS3#
DQMB4
DQMB S# CKE
DQ32
DQ33
DQ34
DQ35
DQMB4
DQMB S# CKE
DQ36
DQ37
DQ38
DQ39
DQMB5
DQMB S# CKE
DQ40
DQ41
DQ42
DQ43
DQMB5
DQMB S# CKE
DQ44
DQ45
DQ46
DQ47
DQMB5
DQMB S# CKE
CB4
CB5
CB6
CB7
DQMB6
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
U1_0
U1_1
U10_0
U10_1
U2_0
U2_1
U11_0
U11_1
U3_0
U3_1
U12_0
U12_1
U4_0
U4_1
U13_0
U13_1
U5_0
U5_1
U14_0
U14_1
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
U6_0
U6_1
DQ48
DQ49
DQ50
DQ51
DQMB6
U15_0
U15_1
DQMB S# CKE
DQ52
DQ53
DQ54
DQ55
DQMB7
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
U7_0
U7_1
U16_0
U16_1
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
U8_0
U8_1
DQ56
DQ57
DQ58
DQ59
DQMB7
U17_0
U17_1
DQMB S# CKE
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
DQMB S# CKE
I/O 0
I/O 1
I/O 2
I/O 3
U9_0
U9_1
U18_0
U18_1
C
orporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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