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5962-8753904LX: 产品描述UV PLD, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24; 产品类别可编程逻辑器件可编程逻辑; 文件大小75KB，共3页; 制造商Cypress(赛普拉斯)

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5962-8753904LX概述

UV PLD, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24

5962-8753904LX规格参数

参数名称	属性值
零件包装代码	DIP
包装说明	DIP,
针数	24
Reach Compliance Code	unknown
ECCN代码	3A001.A.2.C
架构	PAL-TYPE
JESD-30 代码	R-GDIP-T24
专用输入次数	11
I/O 线路数量	10
端子数量	24
最高工作温度	125 °C
最低工作温度	-55 °C
组织	11 DEDICATED INPUTS, 10 I/O
输出函数	MACROCELL
封装主体材料	CERAMIC, GLASS-SEALED
封装代码	DIP
封装形状	RECTANGULAR
封装形式	IN-LINE
可编程逻辑类型	UV PLD
传播延迟	20 ns
认证状态	Not Qualified
表面贴装	NO
技术	CMOS
温度等级	MILITARY
端子形式	THROUGH-HOLE
端子位置	DUAL
Base Number Matches	1

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This is an abbreviated data sheet. Contact a Cypress

representative for complete specifications.

USE ULTRA37000™ FOR

ALL NEW DESIGNS

PALC22V10B

Reprogrammable CMOS PAL

Device

Features

• Advanced second generation PAL architecture

• Low power

— 90 mA max. standard

— 100 mA max. military

• CMOS EPROM technology for reprogrammability

• Variable product terms

— 2 x (8 through 16) product terms

• User-programmable macrocell

— Output polarity control

— Individually selectable for registered or combina-

torial operation

— 15 ns commercial and industrial

10 ns t

15 ns t

50 MHz

— 15 ns and “20 ns” military

10/15 ns t

10/17 ns t

15/20 ns t

50/31 MHz

• Up to 22 input terms and 10 outputs

• Enhanced test features

— Phantom array

— Top test

— Bottom test

— Preload

• High reliability

— Proven EPROM technology

— 100% programming and functional testing

• Windowed DIP, windowed LCC, DIP, LCC, PLCC

available

Functional Description

The Cypress PALC22V10B is a CMOS second-generation

programmable logic array device. It is implemented with the

familiar sum-of-products (AND-OR) logic structure and a new

concept, the “Programmable Macrocell.”

The PALC22V10B is executed in a 24-pin 300-mil molded DIP,

a 300-mil windowed cerDIP, a 28-lead square ceramic

leadless chip carrier, a 28-lead square plastic leaded chip

carrier, and provides up to 22 inputs and 10 outputs. When the

windowed cerDIP is exposed to UV light, the 22V10B is erased

and can then be reprogrammed. The programmable macrocell

provides the capability of defining the architecture of each

output individually. Each of the 10 potential outputs may be

specified as “registered” or “combinatorial.” Polarity of each

output may also be individually

Logic Block Diagram (PDIP/CDIP)

CP/I

PROGRAMMABLE

ANDARRAY

(132X 44)

Reset

Macrocell

Preset

I/O9

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

Cypress Semiconductor Corporation

Document #: 38-03018 Rev. *A

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised April 22, 2004

5962-8753904LX相似产品对比

	5962-8753904LX	5962-87539043X	5962-8867005LX	5962-88670053X	5962-8867004LX	5962-8867005KX	5962-88670043X	PALC22V10B-15JI	PALC22V10B-15PC	PALC22V10B-15WMB
描述	UV PLD, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24	UV PLD, 20ns, CMOS, CQCC28, WINDOWED, CERAMIC, LCC-28	OT PLD, CMOS, CDIP24, 0.300 INCH, CERDIP-24	OT PLD, 15ns, CMOS, CQCC28, CERAMIC, LCC-28	OT PLD, CMOS, CDIP24, 0.300 INCH, CERDIP-24	OT PLD, 15ns, CMOS, CDFP24, GLASS SEALED, CERPACK-24	OT PLD, 20ns, CMOS, CQCC28, CERAMIC, LCC-28	OT PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28	OT PLD, 15ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24	UV PLD, 15ns, PAL-Type, CMOS, CDIP24, 0.300 INCH, WINDOWED, CERDIP-24
零件包装代码	DIP	QLCC	DIP	QLCC	DIP	DFP	QLCC	QLCC	DIP	DIP
包装说明	DIP,	WQCCN,	DIP,	QCCN,	DIP,	DFP,	QCCN,	PLASTIC, LCC-28	DIP, DIP24,.3	DIP, DIP24,.3
针数	24	28	24	28	24	24	28	28	24	24
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	not_compliant	not_compliant	not_compliant
JESD-30 代码	R-GDIP-T24	S-CQCC-N28	R-GDIP-T24	S-CQCC-N28	R-GDIP-T24	R-GDFP-F24	S-CQCC-N28	S-PQCC-J28	R-PDIP-T24	R-GDIP-T24
专用输入次数	11	11	11	11	11	11	11	11	11	11
I/O 线路数量	10	10	10	10	10	10	10	10	10	10
端子数量	24	28	24	28	24	24	28	28	24	24
最高工作温度	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	125 °C	85 °C	75 °C	125 °C
最低工作温度	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-55 °C	-40 °C	-	-55 °C
组织	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O	11 DEDICATED INPUTS, 10 I/O
输出函数	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
封装主体材料	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED
封装代码	DIP	WQCCN	DIP	QCCN	DIP	DFP	QCCN	QCCJ	DIP	DIP
封装形状	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR
封装形式	IN-LINE	CHIP CARRIER, WINDOW	IN-LINE	CHIP CARRIER	IN-LINE	FLATPACK	CHIP CARRIER	CHIP CARRIER	IN-LINE	IN-LINE
可编程逻辑类型	UV PLD	UV PLD	OT PLD	OT PLD	OT PLD	OT PLD	OT PLD	OT PLD	OT PLD	UV PLD
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
表面贴装	NO	YES	NO	YES	NO	YES	YES	YES	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	MILITARY	INDUSTRIAL	COMMERCIAL EXTENDED	MILITARY
端子形式	THROUGH-HOLE	NO LEAD	THROUGH-HOLE	NO LEAD	THROUGH-HOLE	FLAT	NO LEAD	J BEND	THROUGH-HOLE	THROUGH-HOLE
端子位置	DUAL	QUAD	DUAL	QUAD	DUAL	DUAL	QUAD	QUAD	DUAL	DUAL
ECCN代码	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	3A001.A.2.C	-	-	3A001.A.2.C
架构	PAL-TYPE	PAL-TYPE	-	-	PAL-TYPE	-	-	PAL-TYPE	PAL-TYPE	PAL-TYPE
传播延迟	20 ns	20 ns	-	15 ns	20 ns	15 ns	20 ns	15 ns	15 ns	15 ns
Base Number Matches	1	1	1	1	1	1	1	-	-	-
其他特性	-	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS	-	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS	-	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS	10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS
最大时钟频率	-	31.2 MHz	-	50 MHz	-	50 MHz	31.2 MHz	50 MHz	50 MHz	50 MHz
长度	-	11.43 mm	-	11.43 mm	-	15.367 mm	11.43 mm	11.5316 mm	30.099 mm	31.877 mm
座面最大高度	-	2.8956 mm	-	1.9812 mm	-	2.286 mm	1.9812 mm	4.572 mm	4.826 mm	5.08 mm
最大供电电压	-	5.5 V	-	5.5 V	-	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压	-	4.5 V	-	4.5 V	-	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压	-	5 V	-	5 V	-	5 V	5 V	5 V	5 V	5 V
端子节距	-	1.27 mm	-	1.27 mm	-	1.27 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm
宽度	-	11.43 mm	-	11.43 mm	-	9.652 mm	11.43 mm	11.5316 mm	7.62 mm	7.62 mm

5962-8753904LX

5962-8753904LX概述

5962-8753904LX规格参数

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