H8S/2237 Series,
H8S/2237, H8S/2235, H8S/2233
H8S/2227 Series
H8S/2227, H8S/2225, H8S/2223
Hardware Manual
ADE-602-154A
Rev. 2.0
12/15/98
Hitachi Ltd.
Preface
The H8S/2237 Series and H8S/2227 Series are series of high-performance microcontrollers with a
32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system
configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
PROM (ZTAT™*) and mask ROM versions are available, providing a quick and flexible response
to conditions from ramp-up through full-scale volume production, even for applications with
frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), 8-bit timer unit (TMR),
watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter
(H8S/2237 Series only), and I/O ports.
In addition, an on-chip data transfer controller (DTC) is provided, enabling high-speed data
transfer without CPU intervention.
Use of the H8S/2237 Series or H8S/2227 Series enables compact, high-performance systems to be
implemented easily.
This manual describes the hardware of the H8S/2237 Series and H8S/2227 Series. Refer to the
H8S/2600 Series and H8S/2000 Series Programming Manual
for a detailed description of the
instruction set.
Note: * ZTAT is a registered trademark of Hitachi, Ltd.
On-Chip Peripheral Functions
Series
Product Names
Bus controller (BSC)
Data transfer controller (DTC)
16-bit timer pulse unit (TPU)
8-bit timer unit (TMR)
Watchdog timer (WDT)
Serial communication interface (SCI)
A/D converter
D/A converter
PC break controller
H8S/2237 Series
H8S/2237, H8S/2235,
H8S/2233
(16 bits)
Available
×
6
×
2
×
2
×
4
×
8
×
2
×
2
H8S/2227 Series
H8S/2227, H8S/2225,
H8S/2223
(16 bits)
Available
×
3
×
2
×
2
×
3
×
8
—
×
2
Contents
Section 1
1.1
1.2
1.3
Overview
...........................................................................................................
Overview............................................................................................................................
Internal Block Diagrams ....................................................................................................
Pin Description...................................................................................................................
1.3.1 Pin Arrangements .................................................................................................
1.3.2 Pin Functions in Each Operating Mode................................................................
1.3.3 Pin Functions ........................................................................................................
1
1
6
8
8
12
20
Section 2
2.1
CPU
..................................................................................................................... 25
25
25
26
27
27
28
33
34
34
35
36
38
39
39
41
42
42
43
45
55
56
56
56
59
63
63
64
65
68
68
i
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Overview............................................................................................................................
2.1.1 Features.................................................................................................................
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU...................................
2.1.3 Differences from H8/300 CPU.............................................................................
2.1.4 Differences from H8/300H CPU ..........................................................................
CPU Operating Modes.......................................................................................................
Address Space....................................................................................................................
Register Configuration.......................................................................................................
2.4.1 Overview...............................................................................................................
2.4.2 General Registers..................................................................................................
2.4.3 Control Registers ..................................................................................................
2.4.4 Initial Register Values ..........................................................................................
Data Formats......................................................................................................................
2.5.1 General Register Data Formats.............................................................................
2.5.2 Memory Data Formats..........................................................................................
Instruction Set ....................................................................................................................
2.6.1 Overview...............................................................................................................
2.6.2 Instructions and Addressing Modes .....................................................................
2.6.3
Table of Instructions Classified by Function.......................................................
2.6.4 Basic Instruction Formats.....................................................................................
2.6.5 Notes on Use of Bit-Manipulation Instructions....................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1 Addressing Mode..................................................................................................
2.7.2 Effective Address Calculation ..............................................................................
Processing States ...............................................................................................................
2.8.1 Overview...............................................................................................................
2.8.2 Reset State ............................................................................................................
2.8.3 Exception-Handling State.....................................................................................
2.8.4 Program Execution State ......................................................................................
2.8.5 Bus-Released State ...............................................................................................
2.9
2.8.6 Power-Down State ................................................................................................
Basic Timing......................................................................................................................
2.9.1 Overview...............................................................................................................
2.9.2 On-Chip Memory (ROM, RAM) .........................................................................
2.9.3 On-Chip Supporting Module Access Timing.......................................................
2.9.4 External Address Space Access Timing...............................................................
68
69
69
69
71
72
Section 3
3.1
MCU Operating Modes
................................................................................. 73
73
73
74
74
74
75
77
77
77
78
78
79
79
3.2
3.3
3.4
3.5
Overview............................................................................................................................
3.1.1 Operating Mode Selection ....................................................................................
3.1.2 Register Configuration .........................................................................................
Register Descriptions.........................................................................................................
3.2.1 Mode Control Register (MDCR) ..........................................................................
3.2.2 System Control Register (SYSCR).......................................................................
Operating Mode Descriptions ............................................................................................
3.3.1 Mode 4 ..................................................................................................................
3.3.2 Mode 5 .................................................................................................................
3.3.3 Mode 6 ..................................................................................................................
3.3.4 Mode 7 ..................................................................................................................
Pin Functions in Each Operating Mode.............................................................................
Address Map in Each Operating Mode .............................................................................
Section 4
4.1
Exception Handling
........................................................................................ 83
83
83
84
84
86
86
86
87
89
89
90
91
92
93
94
4.2
4.3
4.4
4.5
4.6
4.7
Overview............................................................................................................................
4.1.1 Exception Handling Types and Priority ...............................................................
4.1.2 Exception Handling Operation .............................................................................
4.1.3 Exception Sources and Vector Table ...................................................................
Reset...................................................................................................................................
4.2.1 Overview...............................................................................................................
4.2.2 Reset Types...........................................................................................................
4.2.3 Reset Sequence.....................................................................................................
4.2.4 Interrupts after Reset.............................................................................................
4.2.5 State of On-Chip Supporting Modules after Reset Release .................................
Traces.................................................................................................................................
Interrupts ............................................................................................................................
Trap Instruction .................................................................................................................
Stack Status after Exception Handling ..............................................................................
Notes on Use of the Stack..................................................................................................
Section 5
5.1
Interrupt Controller
......................................................................................... 95
Overview............................................................................................................................ 95
5.1.1 Features................................................................................................................. 95
5.1.2 Block Diagram...................................................................................................... 96
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