Low Skew, 1-to-8 Differential/LVCMOS-to-
LVCMOS Fanout Buffer
Data Sheet
8308I
G
ENERAL
D
ESCRIPTION
The 8308I is a low-skew, 1-to-8 Fanout Buffer. The 8308I has two
selectable clock inputs. The CLK, nCLK pair can accept most
differential input levels. The LVCMOS_CLK can accept LVCMOS
or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs
are designed to drive 50Ω series or parallel terminated transmission
lines. The effective fanout can be increased from 8 to 16 by utilizing
the ability of the outputs to drive two series terminated transmission
lines.
The 8308I is characterized for 3.3V core/3.3V output,
3.3V core/2.5V output or 2.5V core/2.5V output operation.
Guaranteed output and part-part skew characteristics make the
8308I ideal for those clock distribution applications requiring well
defined performance and repeatability.
F
EATURES
•
Eight LVCMOS/LVTTL outputs, (7Ω typical output impedance)
•
Selectable LVCMOS_CLK or differential CLK, nCLK inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Maximum Output Frequency: 350MHz
•
Output Skew: (3.3V± 5%): 100ps (maximum)
•
Part to Part Skew: (3.3V± 5%): 1ns (maximum)
•
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
•
-40°C to 85°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
B
LOCK
D
IAGRAM
CLK_EN
Pullup
D
Q
LE
1
P
IN
A
SSIGNMENT
Q0
GND
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
Q1
V
DDO
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
DDO
Q2
GND
Q3
V
DDO
Q4
GND
Q5
V
DDO
Q6
GND
Q7
LVCMOS_CLK
Pullup
CLK
Pullup
nCLK
Pulldown
Pullup
Q0
0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLK_SEL
8308I
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.925mm body package
G Package
Top View
OE
Pullup
©2015 Integrated Device Technology, Inc
1
December 10, 2015
8308I Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 11, 13, 15,
17, 19, 21, 23
2, 10, 14, 18, 22
3
4
5
6
7
8
9
12, 16, 20, 24
Name
Q0, Q1, Q7, Q6,
Q5, Q4,Q3, Q2
GND
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
V
DDO
Output
Power
Input
Input
Input
Input
Input
Input
Power
Power
Pullup
Pullup
Pullup
Pullup
Pullup
Type
Description
Clock outputs. LVCMOS / LVTTL interface levels.
Power supply ground.
Clock select input. Selects LVCMOS clock input when HIGH.
Selects CLK, nCLK inputs when LOW. See Table 3A.
LVCMOS / LVTTL interface levels.
Clock input. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Clock enable. LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
See Table 3B.
Power supply pin.
Output supply pins.
Pulldown Inverting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
Test Conditions
Minimum
Typical
4
12
51
51
7
12
Maximum
Units
pF
pF
kΩ
kΩ
Ω
T
ABLE
3A. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0
1
Clock Input
CLK, nCLK is selected
LVCMOS_CLK is selected
T
ABLE
3B. OE S
ELECT
F
UNCTION
T
ABLE
Control Input
OE
0
1
Output Operation
Outputs Q0:Q7 are in Hi-Z (disabled)
Outputs Q0:Q7 are active (enabled)
T
ABLE
3C. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
0
0
0
0
0
1
1
LVCMOS_CLK
—
—
—
—
—
—
0
1
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
—
—
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
—
—
Outputs
Q0:Q7
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
Non Inverting
Non Inverting
NOTE 1: Please refer to the Application Information section, “Wiring the Differential Input to Accept Single Ended Levels”.
©2015 Integrated Device Technology, Inc
2
December 10, 2015
8308I Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°
TO
85°
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
46
11
Units
V
V
mA
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°
TO
85°
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
46
10
Units
V
V
mA
mA
T
ABLE
4C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
, V
DDO
= 2.5V±5%, T
A
= -40°
TO
85°
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
43
10
Units
V
V
mA
mA
©2015 Integrated Device Technology, Inc
3
December 10, 2015
8308I Data Sheet
T
ABLE
4D. DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°
TO
85°
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
V
PP
V
CMR
Parameter
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
CLK, nCLK
LVCMOS
LVCMOS_CLK
CLK_EN, OE
V
IN
= V
DD
or V
IN
= GND
I
OH
= -24mA
I
OL
= 24mA
I
OL
= 12mA
0.15
2.4
0.55
0.30
1.3
V
DD
- 0.85
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
0.8
300
Units
V
V
V
µA
V
V
V
V
V
Input Common Mode Voltage;
CLK, nCLK
GND + 0.5
NOTE 2, 3
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to V
DDO
/2.
See Parameter Measurement section, “3.3V Output Load AC Test Circuit”.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
T
ABLE
4E. DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°
TO
85°
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
V
PP
V
CMR
Parameter
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
CLK, nCLK
LVCMOS
LVCMOS_CLK
CLK_EN, OE
V
IN
= V
DD
or V
IN
= GND
I
OH
= -15mA
I
OL
= 15mA
0.15
1.8
0.6
1.3
V
DD
- 0.85
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
0.8
300
Units
V
V
V
µA
V
V
V
V
Input Common Mode Voltage;
CLK, nCLK
GND + 0.5
NOTE 2, 3
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to V
DDO
/2.
See Parameter Measurement section, “3.3V Output Load AC Test Circuit”.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
©2015 Integrated Device Technology, Inc
4
December 10, 2015
8308I Data Sheet
T
ABLE
4F. DC C
HARACTERISTICS
,
V
DD
, V
DDO
= 2.5V±5%, T
A
= -40°
TO
85°
Symbol
V
IH
V
IL
I
IN
V
OH
V
OL
V
PP
V
CMR
Parameter
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
CLK, nCLK
LVCMOS
LVCMOS_CLK
CLK_EN, OE
V
IN
= V
DD
or V
IN
= GND
I
OH
= -15mA
I
OL
= 15mA
0.15
1.8
0.6
1.3
V
DD
- 0.85
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
0.7
300
Units
V
V
V
µA
V
V
V
V
Input Common Mode Voltage;
CLK, nCLK
GND + 0.5
NOTE 2, 3
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to V
DDO
/2.
See Parameter Measurement section, “3.3V Output Load AC Test Circuit”.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°
TO
85°
Symbol
f
OUT
t
PD
Parameter
Output Frequency
Propagation Delay;
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
Test Conditions
ƒ
≤
350MHz
ƒ
≤
350MHz
Measured on rising edge @V
DDO
/2
Measured on rising edge @V
DDO
/2
0.8V to 2V
ƒ
≤
150MHz, Ref = CLK, nCLK
0.2
45
Minimum
Typical
Maximum
350
4
4
100
1
1
55
5
Units
MHz
ns
ns
ps
ns
ns
%
ns
2
2
tsk(o)
tsk(pp)
t
R
/ t
F
odc
t
PZL
, t
PZH
t
PLZ
, t
PHZ
Output Skew; NOTE 3, 7
Part-to-Part Skew; NOTE 4, 7
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
5
ns
CLK_EN to CLK,
1
ns
Clock Enable
nCLK
t
S
Setup Time;
CLK_EN to LVC-
NOTE 6
0
ns
MOS_CLK
CLK, nCLK to
0
ns
Clock Enable
CLK_EN
Hold Time;
t
H
LVCMOS_CLK
NOTE 6
1
ns
to CLK_EN
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to V
DDO
/2 of the output.
NOTE 2: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
©2015 Integrated Device Technology, Inc
5
December 10, 2015
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