HD66107T
(LCD Driver for High Voltage)
Description
The HD66107T is a multi-output, high duty ratio
LCD driver used for large capacity dot matrix LCD
panels. It consists of 160 LCD drive circuits with
a display duty ratio up to 1/480: the seven
HD66107Ts can drive a 640
×
480 dots LCD
panel. Moreover, the LCD driver enables interfaces
with various LCD controllers due to a built-in
automatic generator of chip enable signals. Use of
the HD66107T can help reduce the cost of an
LCD-panel configuration, since it reduces the
number of LCD drivers, compared with use of the
HD61104 and HD61105.
Features
•
•
•
•
•
•
•
Column and row driver
160 or 80 LCD drive circuits
Multiplexing duty ratios: 1/100 to 1/480
4-bit and 8-bit parallel data transfer
Internal automatic chip enable signal generator
Internal standby mode
Recommended LCD controller LSIs:
HD63645F, HD64645F, and HD64646FS
(LCTC), HD66840/HD66841 (LVIC), HD66850
(CLINE)
• Power supply voltage
— Internal logic: +5 V ± 10%
— LCD drive circuit: 14.0 to 37.0 V
• Operation frequency: 8.0 MHz (max.)
• CMOS process
• 192-pin TCP
Ordering Information
Type No.
HD66107T11
HD66107T24
HD66107T12
HD66107T00
HD66107T01
HD66107T25
Number of
Outputs
160
160
160
160
80
80
Outer Lead
Pitch (µm)
180
180
250
280
280
280
Material of Tape
*2
Kapton
Upilex
Kapton
Kapton
Kapton
Kapton
12 perforated holes
8 perforated holes
Note
Notes: 1. “Kapton” is a trademark of Dupont, Ltd.
“Upilex” is a trademark of Ube Industries, Ltd.
2. The details of TCP pattern are shown in “The Information of TCP.”
HD66107T
Pin Description
Power Supply
V
CC
, GND:
V
CC
supplies power to the internal
logic circuits. GND is the logic and drive ground.
V
LCD
:
V
LCD
supplies power to the LCD drive
circuit.
V
1L
, V
1R
, V
2L
, V
2R
, V
3L
, V
3R
, V
4L
, V
4R
:
V
1
to
V
4
supply power for driving an LCD (figure 1).
Control Signal
CL1:
The LSI latches data at the negative edge of
CL1 when the LSI is used as a column driver. Fix
to GND when the LSI is used as a row driver.
CL2:
The LSI latches display data at the negative
edge of CL2 when the LSI is used as a column
driver, and shifts line select data at the negative
edge when it is used as a row driver.
Table 1
Symbol
V
CC
GND
V
LCD
V1L, R
V2L, R
V3L, R
V4L, R
CL1
CL2
M
D
0
–D
7
SHL
CH2
BS
TEST
Y1–Y160
E
CAR
CH1
Pin Function
Pin No.
167
161, 186, 187
166, 192
191, 165
188, 162
190, 164
189, 163
183
184
182
174–181
172
171
173
185
1–160
169
168
170
Pin Name
V
CC
Ground
V
LCD
V1L, V1R
V2L, V2R
V3L, V3R
V4L, V4R
Clock 1
Clock 2
M
DATA0–DATA7
Shift left
Channel 2
Bus select
TEST
Y1–Y160
Enable
Carry
Channel
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Output
Input
Input/Output
V1
V3
V4
V2
V1, V2: Selected level
V3, V4: Nonselected level
Figure 1 Power Supply for Driving an LCD
1085
HD66107T
M:
M changes LCD drive outputs to AC.
D
0
–D
7
:
D
0
–D
7
input display data for the column
driver (table 2).
SHL:
SHL controls the shift direction of display
data and line select data (figure 2, table 3).
E:
E
inputs the enable signal when the LSI is used
as a column driver (CH1 = V
CC
).
The LSI is disabled when
E
is high and enabled
when low.
E
inputs scan data when the LSI is used
as a row driver (CH1 = GND). When HD66107Ts
are connected in cascade,
E
connects with
CAR
of
the preceding LSI.
CAR:
CAR
outputs the enable signal when the
LSI is used as a column driver (CH1 = V
CC
).
CAR
outputs scan data when the LSI is used as a
row driver (CH1 = GND). When HD66107Ts are
connected in cascade,
CAR
connects with
E
of the
next LSI.
CH1:
CH1 selects the driver function. The chip
devices are columns when CH1 = V
CC
, and rows
when CH1 = GND.
CH2:
CH2 selects the number of output data bits.
The number of output data bits is 160 when CH2 =
GND, and 80 when CH2 = V
CC
.
BS:
BS selects the number of input data bits. When
BS = V
CC
, the chip latches 8-bits data. When BS =
GND, the chip latches 4-bits data via D
0
to D
3
. Fix
D
4
through D
7
to GND.
TEST:
Used for testing. Fixed to GND, otherwise.
Table 2
Relation between Display Data
and LCD State
LCD Output
V1L, R/V2L, R
Nonselected level
LCD
On
Off
Display Data
1 (= high level)
0 (= low level)
Table 3
Relation between SHL and Scan Direction of Selected Line
(When LSI Is Used as Row Driver)
Shift Direction of Shift Register
E→
E→
1→
2→
3→
4 ----------→160
Scan Direction of Selected Line
Y1→
Y2→
Y3→
Y4 ---------→Y160
SHL
V
CC
GND
160→ 159→ 158→ 157 ----------→1
Y160→Y159→Y158→Y157 ---------→Y1
Y157
Y158
Y159
Y160
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D0
D1
D2
D3
D0
D1
D2
D3
1st data
2nd data
Last data
Last data
D0
D1
D2
D3
D0
D1
D2
D3
When SHL = GND
When SHL = V
CC
Figure 2 Relation between SHL and Data Output
1086
D0
D1
D2
D3
D0
D1
D2
D3
2nd data
1st data
Y157
Y158
Y159
Y160
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
HD66107T
LCD Drive Interface
Y1–Y160:
Each Y outputs one of the four voltage
levels—V
1
, V
2
, V
3
, V
4
—according to the combi-
nation of M and display data (figure 3).
M
1
D
Y output level
V
1
1
0
1
0
0
M
1
D
Y output level
V
2
1
0
1
0
0
V
3
V
2
V
4
V
3
V
1
V
4
When Used as a Column Driver
When Used as a Row Driver
Figure 3 Selection of LCD Driver Output Level
1087
157
158
159
160
CH1
SHL
CL2
160-bit latch and bidirectional
shift register
157
158
159
160
BS
(4-bit
×
40)
(8-bit
×
20)
D
0
–D
7
Logic
Selector
TEST
Test
circuit
Controller
157
158
159
160
1088
Y
158
Y
160
Y
157
Y
159
V
4
R
V
3
R
V
2
R
V
1
R
V
LCD
LCD drive circuit
V
CC
GND
CH2
Latch circuit 2
Logic
CAR
Latch circuit 1
HD66107T
Block Diagram
V
1L
V
2L
V
3L
V
4L
Y
1
Y
2
Y
3
Y
4
M
1 2 3 4
E
Logic
1 2 3 4
Logic
CL1
1 2 3 4
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