1Mx4-Bit Dynamic RAM
HYB314400BJ/BJL-50/-60/-70
Advanced Information
•
•
•
•
1 048 576 words by 4-bit organization
0 to 70 °C operating temperature
Fast Page Mode Operation
Performance:
-50
tRAC
tCAC
tAA
tRC
tPC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Fast page mode cycle time
50
13
25
95
35
-60
60
15
30
110
40
-70
70
20
35
130
45
ns
ns
ns
ns
ns
•
Fast access and cycle time
Single + 3.3 V (± 0.3 V) supply with a built-in
V
bb
generator
Low power dissipation
max. 252 mW active (-50 version)
max. 216 mW active (-60 version)
max. 198 mW active (-70 version)
Standby power dissipation:
7,2 mW max.standby (LVTTL)
3,6 mW max.standby (LVCMOS)
720
µW
max. standby (LVCMOS) for Low Power Versions
Output unlatched at cycle end allows two-dimensional chip selection
Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh,
hidden refresh and test mode capability
All inputs and outputs LVTTL-compatible
1024 refresh cycles / 16 ms
1024 refresh cycles / 128 ms for Low Power Version
Plastic Packages: P-SOJ-26/20-5 with 300 mil width
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Semiconductor Group
1
3.96
HYB314400BJ/BJL-50/-60/-70
3.3V 1Mx4 DRAM
The HYB 314400BJ/BJL is the new generation dynamic RAM organized as 1 048 576 words by 4-
bit. The HYB 314400BJ/BJL utilizes CMOS silicon gate process as well as advances circuit
techniques to provide wide operation margins, both internally and for the system user. Multiplexed
address inputs permit the HYB 314400BJ/BJL to be packed in a standard plastic P-SOJ-26/20
package. This package size provides high system bit densities and is compatible with commonly
used automatic testing and insertion equipment. System oriented features include single + 3.3 V
(± 0.3 V ) power supply, direct interfacing with high performance logic device families.
Ordering Information
Type
HYB 314400BJ-50
HYB 314400BJ-60
HYB 314400BJ-70
HYB 314400BJL-50
HYB 314400BJL-60
HYB 314400BJL-70
Ordering Code
Q67100-Q2027
Q67100-Q2029
Q67100-Q2031
on request
on request
on request
Package
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
P-SOJ-26/20-5
Descriptions
3.3V DRAM
(access time 50 ns)
3.3V DRAM
(access time 60 ns)
3.3V DRAM
(access time 70 ns)
3.3V Low Power DRAM
(access time 50 ns)
3.3V Low Power DRAM
(access time 60 ns)
3.3V Low Power DRAM
(access time 70 ns)
Pin Names
A0-A9
RAS
CAS
WE
OE
I/O1
-
I/O4
Address Input
Row Address Strobe
Column Address
Strobe
Read/Write Input
Output Enable
Data Input/Output
Power Supply
(+ 3.3 V)
Ground (0 V)
No Connection
I/O1
I/O2
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
Vss
I/O4
I/O3
CAS
OE
V
CC
V
SS
N.C.
A0
A1
A2
A3
VCC
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
P-SOJ-26/20-5
Semiconductor Group
2
HYB314400BJ/BJL-50/-60/-70
3.3V 1Mx4 DRAM
I/O1 I/O2 I/O3 I/O4
WE
CAS
.
&
Data in
Buffer
No. 2 Clock
Generator
Data out
Buffer
OE
4
4
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
Column
Address
Buffer(10)
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
4
Refresh
Counter (10)
1024
x4
Memory Array
1024x1024x4
Row
Address
Buffers(10)
10
Row
Decoder
1024
RAS
No. 1 Clock
Generator
Block Diagram
Semiconductor Group
3
HYB314400BJ/BJL-50/-60/-70
3.3V 1Mx4 DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 °C
Storage temperature range......................................................................................– 55 to + 150 °C
Input/output voltage ............................................................................... – 1 to min (Vcc+0.5, 4.6) V
Power Supply voltage .................................................................................................. – 1 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V ,
t
T
= 5 ns
Parameter
Input high voltage
Input low voltage
TTL Output high voltage (
I
OUT
= – 2 mA)
TTL Output low voltage (
I
OUT
= 2 mA)
CMOS Output high voltage (
I
OUT
= - 100
µA)
CMOS Output low voltage (
I
OUT
= 100
µA)
Input leakage current, any input
(0 V <
V
in
< Vcc + 0.3 V, all other input = 0 V)
Output leakage current
(DO is disabled, 0 <
V
OUT
<
V
cc
)
Average
V
CC
supply current
-50 version
-60 version
-70 version
Standby
V
CC
supply current
(RAS = CAS = WE =
V
ih
)
Average
V
CC
supply current during RAS-only
refresh cycles
-50 version
-60 version
-70 version
Average
V
CC
supply current during fast page
mode operation
-50 version
-60 version
-70 version
Symbol
Limit Values
min.
max.
Vcc+0.5
0.8
–
0.4
0.2
10
10
2.0
– 1.0
2.4
–
-
– 10
– 10
Unit Test
Condition
V
V
V
V
V
V
µA
µA
mA
_
–
–
70
60
55
2
mA
mA
_
–
–
70
60
55
mA
–
–
50
45
40
2) 3)4)
–
2)4)
1)
1)
2) 3)4)
1)
1)
1)
1)
V
ih
V
il
V
oh
V
ol
V
oh
V
ol
I
I(L)
I
o(L)
I
CC1
VCC-0.2 -
I
CC2
I
CC3
–
I
CC4
Semiconductor Group
4
HYB314400BJ/BJL-50/-60/-70
3.3V 1Mx4 DRAM
DC Characteristics
(cont’d)
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 3.3 V
±
0.3 V ,
t
T
= 5 ns
Parameter
Standby
V
CC
supply current
(RAS = CAS = WE =
V
CC
– 0.2 V)
Average
V
CC
supply current during
CAS before RAS refresh mode
-50 version
-60 version
-70 version
For Low Power Version only:
Battery backup current (average power supply
current in battery backup mode):
(CAS = CAS before RAS cycling or 0.2 V,
WE =
V
CC
– 0.2 V or 0.2 V,
A0 to A10 =
V
CC
– 0.2 V or 0.2 V;
DI =
V
CC
– 0.2 V or 0.2 V or open,
t
RC
= 125
µs,
t
RAS
=
t
RAS
min = 1
µs)
Symbol
Limit Values
min.
max.
1
200
–
Unit Test
Condition
mA
µA
mA
–
–
–
70
60
55
300
µA
–
1)
L-version
2)4)
I
CC5
I
CC6
I
CC7
–
Capacitance
T
A
= 0 to 70 °C;
V
CC
= 3.3 V
±
0.3 V;
f
= 1 MHz
Parameter
Input capacitance (A0 to A9)
Input capacitance (RAS, CAS, WE,OE)
Output capacitance (IO1 to
IO4)
Symbol
Limit Values
min.
max.
5
7
7
pF
pF
pF
–
–
–
Unit
C
i1
C
i2
C
io
Semiconductor Group
5
嵌入式系统
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