VSP
320
0
VSP3200
VSP3210
www.ti.com
CCD SIGNAL PROCESSOR FOR
SCANNER APPLICATIONS
FEATURES
F
INTEGRATED TRIPLE-CORRELATED
DOUBLE SAMPLER
F
OPERATION MODE SELECTABLE:
1-Channel, 3-Channel CCD Mode, 8Msps
F
PROGRAMMABLE GAIN AMPLIFIER:
0dB to +13dB
F
SELECTABLE OUTPUT MODES:
Normal/Demultiplexed
F
OFFSET CONTROL RANGE: ±500mV
F
+3V, +5V Digital Output
F
LOW POWER: 300mW (typ)
F
LQFP-48 SURFACE-MOUNT PACKAGE
DESCRIPTION
The VSP3200 and VSP3210 are complete CCD image
processors that operate from single +5V supplies.
This complete image processor includes three Corre-
lated Double Samplers (CDSs) and Programmable
Gain Amplifiers (PGAs) to process CCD signals.
The VSP3200 is interface compatible with the
VSP3210, which is a 16-bit, one-chip product.
The VSP3210 is pin-to-pin compatible with VSP3100,
when in demultiplexed output mode.
The VSP3200 and VSP3210 can be operated from 0°C
to +85°C, and are available in LQFP-48 packages.
CLP
CK1 CK2
ADCCK
TP0
V
REF
Reference
Circuit
Timing Generator
Clamp
RINP
CDS
AGND
6
PGA
CM
REFP
REFN
10
Clamp
GINP
10-Bit
DAC
OE
V
DRV
CDS
PGA
MUX
16-Bit
A/D
Converter
16
Digital
Output
Control
B0-B15
(A0-A2, D0-D9)
10
Clamp
BINP
10-Bit
DAC
6
CDS
PGA
Gain
Control
Register
R
3
Offset
Register
R
G
B
10
10-Bit
DAC
Configuration
Register
6
8
Register
Port
10
P/S
WRT
RD
SCLK
SD
G
B
6
VSP3200
Copyright © 2000, Texas Instruments Incorporated
SBMS012A
Printed in U.S.A. November, 2000
SPECIFICATIONS
At T
A
= 25°C, V
CC
= +5.0V, V
DRV
= +3.0V, Conversion Rate (f
ADCCK
) = 6MHz, f
CK1
= 2MHz, f
CK2
= 2MHz, PGA Gain = 1, normal output mode, no output load, unless
otherwise specified.
VSP3200Y
VSP3210Y
PARAMETER
RESOLUTION
CONVERSION CHARACTERISTICS
1-Channel CCD Mode, Max
3-Channel CCD Mode, Max
DIGITAL INPUTS
Logic Family
Convert Command
High-Level Input Current (V
IN
= V
CC
)
Low-Level Input Current (V
IN
= 0V)
Positive-Going Threshold Voltage
Negative-Going Threshold Voltage
Input Limit
Input Capacitance
ANALOG INPUTS
Full-Scale Input Range
Input Capacitance
Input Limits
External Reference Voltage Range
Reference Input Resistance
DYNAMIC CHARACTERISTICS
Integral Non-Linearity (INL)
Differential Non-Linearity (DNL)
No Missing Codes
Output Noise
PSRR
DC ACCURACY
Zero Error
Gain Error
Offset Control Range
DIGITAL OUTPUTS
Logic Family
Logic Coding
Digital Data Output Rate, Max
V
DRV
Supply Range
Output Voltage, V
DRV
= +5V
Low Level
High Level
Low Level
High Level
Output Voltage, V
DRV
= +3V
Low Level
High Level
Output Enable Time
3-State Enable Time
Output Capacitance
Data Latency
Data Output Delay
POWER-SUPPLY REQUIREMENTS
Supply Voltage: V
CC
Supply Current: I
CC
(No Load)
Power Dissipation (No Load)
TEMPERATURE RANGE
Operation Temperature
Thermal Resistance
V
IN
= 500mV (V
REF
= 1.0V)
PGA Gain = 0dB, Input Grounded
V
CC
= +5V, ±0.25V
CMOS
Rising Edge of ADCCK Clock
20
20
2.20
0.80
AGND – 0.3
5
0.5
10
AGND – 0.3
0.25
800
±8
±1.5
Guaranteed
8.0
0.04
0.8
1.5
10-Bit Control DAC
Output Voltage Range
±500
CMOS
Straight Binary
Normal Mode
Demultiplexed Mode
8
8
+2.7
MHz
MHz
V
V
V
V
V
V
V
ns
ns
pF
Clock Cycles
ns
V
mA
mA
mW
mW
°C
°C/W
V
CC
+ 0.3
1.75
3.5
V
CC
+ 0.3
µA
µA
V
V
V
pF
Vp-p
pF
V
V
W
LSB
LSB
LSBs rms
% FSR
% FS
% FS
mV
CONDITIONS
MIN
TYP
16
8
8
MAX
UNITS
Bits
MHz
MHz
Start Conversion
+5.3
+0.1
I
OL
= 50µA
I
OH
= 50µA
I
OL
= 1.6mA
I
OH
= 0.5mA
I
OL
= 50µA
I
OH
= 50µA
Output Enable = LOW
Output Enable = HIGH
+4.6
+0.4
+2.4
+0.1
+2.5
20
2
5
8
40
10
C
L
= 15pF
4.7
3-Ch
1-Ch
3-Ch
1-Ch
CCD
CCD
CCD
CCD
Mode
Mode
Mode
Mode
0
100
5
70
60
350
300
12
5.3
LQFP-48
+85
θ
JA
2
VSP3200, 3210
SBMS012A
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage: V
CC
, V
DRV
............................................................... +6.5V
Supply Voltage Differences: Among V
CC
......................................... ±0.1V
GND Voltage Differences: Among GNDA ........................................ ±0.1V
Digital Input Voltage ............................................... –0.3V to (V
CC
+ 0.3V)
Analog Input Voltage .............................................. –0.3V to (V
CC
+ 0.3V)
Input Current (Any Pins Except Supplies) ..................................... ±10mA
Ambient Temperature Under Bias ................................. –40°C to +125°C
Storage Temperature .................................................... –55°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR Reflow, peak, 10s) ............................. +235°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
340
SPECIFIED
TEMPERATURE
RANGE
0°C to +85°C
PACKAGE
MARKING
VSP3200Y
ORDERING
NUMBER
(1)
VSP3200Y
VSP3200Y/2K
VSP3210Y
VSP3210Y/2K
TRANSPORT
MEDIA
250-Piece Tray
Tape and Reel
250-Piece Tray
Tape and Reel
PRODUCT
VSP3200Y
PACKAGE
LQFP-48
"
VSP3210Y
"
LQFP-48
"
340
"
0°C to +85°C
"
VSP3210Y
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “VSP3200Y/2K” will get a single 2000-piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT
VSP3200Y
PACKAGE
DEM-VSP3200Y
VSP3200, 3210
SBMS012A
3
PIN CONFIGURATION
Top View
LQFP
36
B12 (A2) 37
B13 38
B14 39
B15 (MSB) 40
V
DRV
41
V
CC
42
V
CC
43
AGND 44
TP0 45
V
REF
46
V
CC
47
REFN 48
1
35
34
33
32
31
30
29
28
27
26
25
24 OE
23 V
CC
22 SCLK
21 SD
20 P/S
19 WRT
VSP3200Y
B0 (D0) LSB
18 RD
17 AGND
16 CK2
15 CK1
14 ADCCK
13 V
CC
12
B11 (A1)
B10 (A0)
B9 (D9)
B8 (D8)
B7 (D7)
B6 (D6)
B5 (D5)
B4 (D4)
B3 (D3)
B2 (D2)
10
2
3
4
5
6
7
8
9
11
B1 (D1)
V
CC
REFP
RINP
AGND
AGND
AGND
AGND
BINP
PIN DESCRIPTIONS (VSP3200Y)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DESIGNATOR
CM
REFP
AGND
AGND
RINP
AGND
GINP
AGND
BINP
AGND
V
CC
CLP
V
CC
ADCCK
CK1
CK2
AGND
RD
WRT
P/S
SD
SCLK
V
CC
OE
B0 (D0) LSB
B1 (D1)
B2 (D2)
B3 (D3)
TYPE
AO
AO
P
P
AI
P
AI
P
AI
P
P
DI
P
DI
DI
DI
P
DI
DI
DI
DI
DI
P
DI
DIO
DIO
DIO
DIO
DESCRIPTION
Common-Mode Voltage
Upper-Level Reference
Analog Ground
Analog Ground
Red Channel Analog Input
Analog Ground
Green Channel Analog Input
Analog Ground
Blue Channel Analog Input
Analog Ground
Analog Power Supply, +5V
Clamp Enable
HIGH = Enable, LOW = Disable
Analog Power Supply, +5V
Clock for A/D Converter Digital Data Output
Sample Reference Clock
Sample Data Clock
Analog Ground
Read Signal for Registers
Write Signal for Registers
Parallel/Serial Port Select
HIGH = Parallel Port, LOW = Serial Port
Serial Data Input
Serial Data Shift Clock
Analog Power Supply, +5V
Output Enable
A/D Output (Bit 0) and Register Data (D0)
A/D Output (Bit 1) and Register Data (D1)
A/D Output (Bit 2) and Register Data (D2)
A/D Output (Bit 3) and Register Data (D3)
PIN
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DESIGNATOR
B4 (D4)
B5 (D5)
B6 (D6)
B7 (D7)
B8 (D8)
B0 LSB
B9 (D9)
B1
B10 (A0)
B2
B11 (A1)
B3
B12 (A2)
B4
B13
B5
B14
B6
B15 MSB
B7 MSB
V
DRV
V
CC
V
CC
AGND
TP0
V
REF
TYPE
DIO
DIO
DIO
DIO
DIO
DO
DIO
DO
DIO
DO
DIO
DO
DIO
DO
DO
DO
DO
DO
DO
DO
P
P
P
P
AO
AIO
DESCRIPTION
A/D Output (Bit 4) and Register Data (D4)
A/D Output (Bit 5) and Register Data (D5)
A/D Output (Bit 6) and Register Data (D6)
A/D Output (Bit 7) and Register Data (D7)
A/D Output (Bit 8) and Register Data (D8)
A/D Output (Bit 0) when Demultiplexed Output Mode
A/D Output (Bit 9) and Register Data (D9)
A/D Output (Bit 1) when Demultiplexed Output Mode
A/D Output (Bit 10) and Register Address (A0)
A/D Output (Bit 2) when Demultiplexed Output Mode
A/D Output (Bit 11) and Register Address (A1)
A/D Output (Bit 3) when Demultiplexed Output Mode
A/D Output (Bit 12) and Register Address (A2)
A/D Output (Bit 4) when Demultiplexed Output Mode
A/D Output (Bit 13)
A/D Output (Bit 5) when Demultiplexed Output Mode
A/D Output (Bit 14)
A/D Output (Bit 6) when Demultiplexed Output Mode
A/D Output (Bit 15)
A/D Output (Bit 7) when Demultiplexed Output Mode
Digital Output Driver Power Supply
Analog Power Supply, +5V
Analog Power Supply, +5V
Analog Ground
A/D Converter Input Monitor Pin (single-ended output)
Reference Voltage Input/Output
INT Ref: Bypass to GND with 0.1µF
EXT Ref: Input Pin for Ref Voltage
Analog Power Supply, +5V
Lower-Level Reference
AGND
GINP
47
48
V
CC
REFN
P
AO
CLP
CM
4
VSP3200, 3210
SBMS012A
PIN CONFIGURATION
Top View
B0, B8 (LSB)
LQFP
B5, B13
B4, B12
B3, B11
B2, B10
B1, B9
NC
NC
NC
NC
NC
36
B6, B14 37
B7, B15 (MSB) 38
NC 39
NC 40
V
DRV
41
V
CC
42
V
CC
43
AGND 44
TP0 45
V
REF
46
V
CC
47
REFN 48
1
CM
35
34
33
32
31
30
29
28
27
26
25
24 OE
23 V
CC
22 SCLK
21 SD
20 AGND
19 WRT
VSP3210Y
NC
18 AGND
17 AGND
16 CK2
15 CK1
14 ADCCK
13 V
CC
2
REFP
3
AGND
4
AGND
5
RINP
6
AGND
7
GINP
8
AGND
9
BINP
10
AGND
11
V
CC
12
CLP
PIN DESCRIPTIONS (VSP3210Y)
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
DESIGNATOR
CM
REFP
AGND
AGND
RINP
AGND
GINP
AGND
BINP
AGND
V
CC
CLP
V
CC
ADCCK
CK1
CK2
AGND
AGND
WRT
AGND
SD
SCLK
V
CC
OE
NC
NC
NC
NC
NC
TYPE
AO
AO
P
P
AI
P
AI
P
AI
P
P
DI
P
DI
DI
DI
P
P
DI
P
DI
DI
P
DI
–
–
–
–
–
DESCRIPTION
Common-Mode Voltage
Upper-Level Reference
Analog Ground
Analog Ground
Red Channel Analog Input
Analog Ground
Green Channel Analog Input
Analog Ground
Blue Channel Analog Input
Analog Ground
Analog Power Supply, +5V
Clamp Enable
HIGH = Enable, LOW = Disable
Analog Power Supply, +5V
Clock for A/D Converter Digital Data Output
Sample Reference Clock
Sample Data Clock
Analog Ground
Analog Ground
Write Signal for Registers
Analog Ground
Serial Data Input
Serial Data Shift Clock
Analog Power Supply, +5V
Output Enable
Should Be Left OPEN
Should Be Left OPEN
Should Be Left OPEN
Should Be Left OPEN
Should Be Left OPEN
PIN
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DESIGNATOR
NC
B0 LSB
B8
B1
B9
B2
B10
B3
B11
B4
B12
B5
B13
B6
B14
B7
B15 MSB
NC
NC
V
DRV
V
CC
V
CC
AGND
TP0
V
REF
TYPE
–
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
–
–
P
P
P
P
AO
AIO
DESCRIPTION
Should Be Left OPEN
A/D Output (Bit 0) LSB
A/D Output (Bit 8)
A/D Output (Bit 1)
A/D Output (Bit 9)
A/D Output (Bit 2)
A/D Output (Bit 10)
A/D Output (Bit 3)
A/D Output (Bit 11)
A/D Output (Bit 4)
A/D Output (Bit 12)
A/D Output (Bit 5)
A/D Output (Bit 13)
A/D Output (Bit 6)
A/D Output (Bit 14)
A/D Output (Bit 7)
A/D Output (Bit 15) MSB
Should Be Left OPEN
Should Be Left OPEN
Digital Output Driver Power Supply
Analog Power Supply, +5V
Analog Power Supply, +5V
Analog Ground
A/D Converter Input Monitor Pin (single-ended output)
Reference Voltage Input/Output
INT Ref: Bypass to GND with 0.1µF
EXT Ref: Input Pin for Ref Voltage
Analog Power Supply, +5V
Lower-Level Reference
47
48
V
CC
REFN
P
AO
VSP3200, 3210
SBMS012A
5
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