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AP1658
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AP165801.EXE
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Implementation of the power management features with
the Keil compiler (SAB C161RI BB)
This Application Note describes the implementation of power management features by
means of the C166 Keil compiler (COMPILER C166 V3.05a, Linker L166 V3.05, Obj.-
Hex. Converter HEX86 FILE CONVERTER V2.0). The power management makes that
microcontroller very useful in power sensitive telecommunication applications.
Author: Wolfgang Boelderl-Ermel / HL COM WN SE
Semiconductor Group
09.98, Rel. 01
Implementation of the power
management features with the Keil compiler
1.
2.
3.
Introduction .............................................................................................................................. 3
Implementation ........................................................................................................................4
Appendix..................................................................................................................................8
AP1658 ApNote - Revision History
Actual Revision : Rel.01
Previous Revison: None
Page of
Page of
Subjects changes since last release)
actual Rel. prev. Rel.
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Implementation of the power
management features with the Keil compiler
1. Introduction
The microcontrollers of the Siemens 16-bit family have been designed to meet the high
performance requirements of real-time embedded control applications. The architecture of
this family has been optimized for high instruction throughput and minimum response time
to external interrupts.
The core of the 16-bit family has been developed with a modular family concept in mind.
All family members execute an efficient control-optimized instruction set. This allows an
easy and quick implementation of new family members with different internal memory
sizes and technologies, different sets of on-chip peripherals and/or different numbers of IO
pins.
The C161RI device is further enhanced by a flexible power management. This power
management mechanism provides effective means to control the power that is consumed
in a certain state of the controller and thus allows the minimization of the overall power
consumption with respect to a given application.
To implement these features it can be made use of both assembler programming and high
level language programming (Keil C). In this application note the main focus lays on a pure
C-language solution. For the assembler solution only hints are given.
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Implementation of the power
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2. Implementation
To make use of the power management at the C161RI it is important to know how we use
the unlock sequence. The correct execution of this unlock sequence is very important for
that feature. To program the power management the registers SYSCON2 and SYSCON3
have to be used.
The power management control registers SYSCON2 and SYSCON3 control functions and
modes which are critical for the C161RI’ operation. For this reason they are locked
s
(except for bitfield SYSRLS in register SYSCON2) after the execution of EINIT (like
register SYSCON) so these vital system functions cannot be changed inadvertently e.g. by
software errors.
However, as these registers control the power management they need to be accessed
during operation to select the appropriate mode. The system control software gets this
access via a special unlock sequence which allows one single write access to either
SYSCON2 or SYSCON3 when executed properly. This provides a maximum of security.
Note: Of course SYSCON2 and SYSCON3 may be read at any time without restrictions.
The unlock sequence is executed by writing defined values to bitfield SYSRLS using
defined instructions (see table below). The instructions of the unlock sequence (including
the intended write access) must be secured with an EXTR instruction (switch to ESFR
space and lock interrupts).
Note: The unlock sequence provides no write access to register SYSCON.
The basic routine to unlock the power management consists of the following assembler
instructions:
EXTR
BFLDL
MOV
BSET
#xH
SYSCON2,#0FH,#09H
SYSCON2,#0003H
SYSCON2.2
;Switch to ESFR space and unlock sequence
;Unlock sequence, step 1 (1001B)
;Unlock sequence, step 2 (0011B)
;Unlock sequence, step 3 (0111B)
The x in the EXTR instruction indicates the number of those instructions which should be
accessed in the ESFR range.
A typical error in executing the unlock sequence occurs if the wrong hardware address is
put into the header file, where SYSCON2 is declared. For the C161RI BB step it must be
the hardware address F1D0h. (The correct instruction is usually in the header file called
reg161RI.h. Syntax: sfr SYSCON2 = 0xF1D0;) This address is located in the ESFR range.
Therefore it has to be taken care that the access to this register is correct. Accesses to this
address are usually performed by the short address and this short address appears both in
the SFR area and in the ESFR area. The C161 will realize the right area by means of the
EXTR instruction.
In addition it has to be taken care about the right bit address of the SYSCON2.2 bit. In our
case we have declared a name for this bit called UNLOCK. Like the SYSCON2 address it
has to be defined in the header file reg161RI.reg. (Syntax: bit UNLOCK = SYSCON2^2;
Attention: the syntax of the Tasking compiler could be different here.)
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Implementation of the power
management features with the Keil compiler
For advanced power management the register SYSCON3 has to be used. A similar code
to SYSCON2 has to be implemented in the header file reg161RI.h - again the hardware
address has to be checked. (Syntax: sfr SYSCON3 = 0xF1D4;)
To add the unlock sequence to the source code it is now made use of intrinsic functions.
These functions are delivered together with the Keil compiler. The declaration of these
functions can be found in the header file intrins.h. This file has to be included in the source
code. The intrinsic functions help the C-language programmer to use C161RI-specific
assembler instructions.
To execute the unlock sequence in the right way it is proposed to use the functions
_bfld_() and _nop_(). After the unlock sequence the "power management instruction" will
be executed. In our example the CPU has to be slowed down. The code has to be
implemented in the following way:
_bfld_(SYSCON2,0x000F,0x0009);
SYSCON2 =
0x03;
UNLOCK
=
1;
_bfld_(SYSCON2, 0x7F00, 0x2900);
/* execute unlock sequence */
/* slow down the CPU */
Note1: The command SYSCON2 = 0x03; writes only to the bits SYSRLS in the register
SYSCON2. (Register SYSCON2 is not unlocked yet.)
Note 2: In the intrinsic function _bfld_() only constant values may be used.
A look at the generated assembler code (use compiler option CD) in the list file shows the
following result:
Hex code Assembler instruction
D1B0
EXTR
#04H
0AE80F09
BFLDL
SYSCON2,#0FH,#09H
E6E80300
MOV
SYSCON2,#03H
2FE8
BSET
UNLOCK
1AE8297F
BFLDH
SYSCON2,#07FH,#029H
;execute unlock sequence
;slow down CPU executed
Note: The command EXTR is added automatically by the compiler. It calculates the correct
number of instructions which use ESFR registers.
An advanced technique to avoid problems with the unlock sequence is to initialize the
bitfield SYSRLS with 0, before executing the unlock sequence. It is strongly recommended
to add the following instructions:
bfld_(SYSCON2,0x000F,0x0000); /* initialize bitfield SYSRLS */
_nop_();
It is very important to add one _nop_() instruction after that initialization. If it is missed the
compiler will be confused and generate the following result (together with unlock sequence
and the instruction for slow down the CPU):
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