HB288448E5/HB288384E5
HB288320E5/HB288256E5
CompactFlash™
448 MByte/384 MByte/320 MByte/256 MByte
ADE-203-1162 (Z)
Preliminary
Rev. 0.0
Feb. 23, 2000
Description
HB288448E5, HB288384E5, HB288320E5, HB288256E5 are CompactFlash™. This card complies with
CompactFlash™ specification, and is suitable for the usage of data storage memory medium for PC or any
other electric equipment and digital still camera. This card is equipped with Hitachi 256 Mega bit Flash
memory. This card is suitable for ISA (Industry Standard Architecture) bus interface standard, and read/write
unit is 1 sector (512 bytes) sequential access. By using this card it is possible to operate good performance for
the system which have CompactFlash
TM
slots.
Note:
CompactFlash™ is a trademark of SanDisk Corporation and is licensed royalty-free to the CFA which
in turn will license it royalty-free to CFA members.
*CFA: CompactFlash™ Association.
Features
•
CompactFlash™ specification standard
50 pin two pieces connector and Type II (5.0 mm)
•
3.3V / 5V single power supply operation
•
Card density is 448 Mega bytes maximum
This card is equipped with Hitachi 256 Mega bit Flash memory
•
3 variations of mode access
Memory card mode
I/O card mode
True IDE mode
•
Internal self-diagnostic program operates at V
CC
power on
•
High reliability based on internal ECC (Error Correcting Code) function
•
Data write is 300,000 cycles
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
HB288448/384/320/256E5
•
Data reliability is 1 error in 10
–14
bits read
•
Auto sleep mode
Card Line Up*
1
Type No.
HB288448E5
HB288384E5
HB288320E5
HB288256E5
Notes: 1.
2.
3.
4.
Card density Capacity*
448 MB
384 MB
320 MB
256 MB
4
Total sectors/ Sectors/
card*
3
track*
2
63
49
56
48
Number of
head
15
15
15
15
Number of
cylinder
927
1021
745
695
448,519,680 byte 876,015
384,222,720 byte 750,435
320,409,600 byte 625,800
256,204,800 byte 500,400
These data are written in ID.
Total tracks = number of head
×
number of cylinder.
Total sectors/card = sectors/track
×
number of head
×
number of cylinder.
It is the logical address capacity including the area which is used for file system.
2
HB288448/384/320/256E5
Card Pin Assignment
Memory card mode
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal name
GND
D3
D4
D5
D6
D7
-CE1
A10
-OE
A9
A8
A7
VCC
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
WP
-CD2
-CD1
D11
D12
D13
D14
I/O
—
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
—
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O card mode
Signal name
GND
D3
D4
D5
D6
D7
-CE1
A10
-OE
A9
A8
A7
VCC
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
-IOIS16
-CD2
-CD1
D11
D12
D13
D14
I/O
—
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
—
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
True IDE mode
Signal name
GND
D3
D4
D5
D6
D7
-CE1
A10
-ATASEL
A9
A8
A7
VCC
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
-IOIS16
-CD2
-CD1
D11
D12
D13
D14
I/O
—
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
—
I
I
I
I
I
I
I
I/O
I/O
I/O
O
O
O
I/O
I/O
I/O
I/O
3
HB288448/384/320/256E5
Memory card mode
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Signal name
D15
-CE2
-VS1
-IORD
-IOWR
-WE
RDY/-BSY
VCC
-CSEL
-VS2
RESET
-WAIT
-INPACK
-REG
BVD2
BVD1
D8
D9
D10
GND
I/O
I/O
I
O
I
I
I
O
—
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
—
I/O card mode
Signal name
D15
-CE2
-VS1
-IORD
-IOWR
-WE
-IREQ
VCC
-CSEL
-VS2
RESET
-WAIT
-INPACK
-REG
-SPKR
-STSCHG
D8
D9
D10
GND
I/O
I/O
I
O
I
I
I
O
—
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
—
True IDE mode
Signal name
D15
-CE2
-VS1
-IORD
-IOWR
-WE
INTRQ
VCC
-CSEL
-VS2
-RESET
IORDY
-INPACK
-REG
-DASP
-PDIAG
D8
D9
D10
GND
I/O
I/O
I
O
I
I
I
O
—
I
O
I
O
O
I
I/O
I/O
I/O
I/O
I/O
—
4
HB288448/384/320/256E5
Card Pin Explanation
Signal name
Direction Pin No.
Description
A10 to A0
I
(PC Card Memory mode)
A10 to A0
(PC Card I/O mode)
A2 to A0
(True IDE mode)
BVD1
I/O
(PC Card Memory mode)
-STSCHG
(PC Card I/O mode)
-PDIAG
(True IDE mode)
BVD2
I/O
(PC Card Memory mode)
-SPKR
(PC Card I/O mode)
-DASP
(True IDE mode)
-CD1, -CD2
O
(PC Card Memory mode)
-CD1, -CD2
(PC Card I/O mode)
-CD1, -CD2
(True IDE mode)
-CE1, -CE2
I
(PC Card Memory mode)
Card Enable
-CE1, -CE2
(PC Card I/O mode)
Card Enable
-CE1, -CE2
(True IDE mode)
-CE2 is used for select the Alternate Status Register
and the Device Control Register while -CE1 is the chip
select for the other task file registers.
7, 32
-CE1 and -CE2 are low active card select signals.
Byte/Word/Odd byte mode are defined by combination
of -CE1, -CE2 and A0.
26, 25
45
18, 19, 20
46
Address bus is A10 to A0. Only A2 to A0 are used,
A10 to A3 should be grounded by the host.
BVD1 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-STSCHG is used for changing the status of
Configuration and status register in attribute area.
-PDIAG is the Pass Diagnostic signal in Master/Slave
handshake protocol.
BVD2 outputs the battery voltage status in the card.
This output line is constantly driven to a high state
since a battery is not required for this product.
-SPKR outputs speaker signals. This output line is
constantly driven to a high state since this product
does not support the audio function.
-DASP is the Disk Active/Slave Present signal in the
Master/Slave handshake protocol.
-CD1 and -CD2 are the card detection signals. -CD1
and -CD2 are connected to ground in this card, so
host can detect that the card is inserted or not.
8, 10, 11, 12, 14, Address bus is A10 to A0. A10 is MSB and A0 is
15, 16, 17, 18,
LSB.
19, 20
5
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