PC100 SDRAM MODULE
KMM374S823CTS
Revision History
[Rev.1] March 24. 1999
Package Dimension changed.
Decoupling Capacitance changed from two 0.1uF to one 0.1uF and one 0.33 uF.
Rev.1 Mar 1999
PC100 SDRAM MODULE
KMM374S823CTS SDRAM DIMM
KMM374S823CTS
8Mx72 SDRAM DIMM with ECC based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung KMM374S823CTS is a 8M bit x 72 Synchronous
Dynamic RAM high density memory module. The Samsung
KMM374S823CTS consists of nine CMOS 8M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. One 0.1uF and one 0.33 uF decoupling capacitors
are mounted on the printed circuit board in parallel for each
SDRAM.
The KMM374S823CTS is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
FEATURE
• Performance range
Part No.
KMM374S823CTS-G8
KMM374S823CTS-GH
KMM374S823CTS-GL
•
•
•
•
•
Max Freq. (Speed)
125MHz (8ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
Burst mode operation
Auto & self refresh capability (4096 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height (1,375mil),
single sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
DD
WE
DQM0
Front
Pin Front Pin
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
DD
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
*CS1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
*CLK1
*A12
V
SS
CKE0
*CS3
DQM6
DQM7
*A13
V
DD
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
V
DD
DQ52
NC
*V
REF
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
*CLK3
NC
**SA0
**SA1
**SA2
V
DD
29 DQM1 57 DQ18 85
58 DQ19 86
30
CS0
59
31
DU
V
DD
87
60 DQ20 88
V
SS
32
61
A0
33
NC
89
62 *V
REF
90
34
A2
63 *CKE1 91
A4
35
64
A6
36
V
SS
92
65 DQ21 93
A8
37
38 A10/AP 66 DQ22 94
67 DQ23 95
BA1
39
68
40
V
DD
V
SS
96
69 DQ24 97
V
DD
41
42 CLK0 70 DQ25 98
71 DQ26 99
43
V
SS
72 DQ27 100
DU
44
73
CS2
45
V
DD
101
46 DQM2 74 DQ28 102
47 DQM3 75 DQ29 103
76 DQ30 104
DU
48
77 DQ31 105
V
DD
49
78
NC
50
V
SS
106
79 CLK2 107
NC
51
80
CB2
52
NC 108
81
CB3
53
WP 109
82 **SDA 110
V
SS
54
55 DQ16 83 **SCL 111
56 DQ17 84
V
DD
112
PIN NAMES
Pin Name
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0, CLK2
CKE0
CS0, CS2
RAS
CAS
WE
DQM0 ~ 7
V
DD
V
SS
*V
REF
SDA
SCL
SA0 ~ 2
WP
DU
NC
Function
Address input (Multiplexed)
Select bank
Data input/output
Check bit (Data-in/data-out)
Clock input
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Power supply for reference
Serial data I/O
Serial clock
Address in EEPROM
Write protection
Don′t use
No connection
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev.1 Mar 1999
PC100 SDRAM MODULE
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
KMM374S823CTS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE should be enabled 1CLK+t
SS
prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
WP pin is connected to V
SS
through 47KΩ Resistor.
When WP is "high", EEPROM Programming will be inhibited and the entire memory will
be write - protected.
Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A11
BA0 ~ BA1
RAS
CAS
WE
DQM0 ~ 7
DQ0 ~ 63
CB0 ~ 7
WP
V
DD
/V
SS
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Check bit
Write protection
Power supply/ground
Rev.1 Mar 1999
PC100 SDRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
CS0
DQM0
KMM374S823CTS
•
DQM
CS
U0
DQM4
DQM
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM6
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U6
DQM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS2
DQM2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U2
DQM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U7
•
DQM
CS
U3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U8
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS
U4
Serial PD
SCL
SDA
A0
A1
A2
•
WP
47KΩ
SA0 SA1 SA2
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
3.3pF
*1
CLK0/2
10Ω
•
•
•
A0 ~ An, BA0 & 1
RAS
CAS
WE
CKE0
10Ω
DQn
V
DD
Vss
•
•
•
•
•
U0/U3
U5/U7
U1/U4
U6/U8
U2
Every DQpin of SDRAM
CLK1/3
One 0.1uF and one 0.33 uF Cap.
To all SDRAMs
per each SDRAM
*1 : For 4 loads, CLK2 only.
10Ω
10pF
Rev.1 Mar 1999
PC100 SDRAM MODULE
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
9
50
KMM374S823CTS
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current (Inputs)
Input leakage current (I/O pins)
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
IL
Min
3.0
2.0
-0.3
2.4
-
-9
-1.5
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
9
1.5
Unit
V
V
V
V
V
uA
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
3,4
Note
Note :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
= 1.4V
±
200 mV)
Pin
Symbol
C
ADD
C
IN
C
CKE
C
CLK
C
CS
C
DQM
C
OUT1
C
OUT2
Min
45
45
40
30
30
5
5
5
Max
65
65
60
40
40
15
15
15
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Address (A0 ~ A11, BA0 ~ BA1)
RAS, CAS, WE
CKE (CKE0)
Clock (CLK0, CLK2)
CS (CS0, CS2)
DQM (DQM0 ~ DQM7)
DQ (DQ0 ~ DQ63)
CB (CB0 ~ CB7)
Rev.1 Mar 1999
实时操作系统RTOS
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