CAT24C256
256-Kb I
2
C CMOS Serial EEPROM
fEATuRES
n
Supports Standard and fast I
2
C Protocol
n
1.8V to 5.5V Supply Voltage Range
n
64-byte Page Write buffer
n
Hardware Write Protection for entire memory
n
Schmitt Triggers and noise Suppression filters
DEVICE DESCRIPTIOn
The CAT24C256 is a 256-Kb Serial CMOS EEPROM,
internally organized as 32,768 words of 8 bits each.
It features a 64-byte page write buffer and supports
both the Standard (00kHz) as well as Fast (400kHz)
I
2
C protocol.
Write operations can be inhibited by taking the WP pin
High (this protects the entire memory).
External address pins make it possible to address up to
eight CAT24C256 devices on the same bus.
on I
2
C bus Inputs (SCl and SDA).
n
low power CMOS technology
n
1,000,000 program/erase cycles
n
100 year data retention
n
Industrial temperature range
n
RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
8-pad TDfn packages
for Ordering Information details, see page 15.
PIn COnfIguRATIOn
PDIP (l)
SOIC (W, X)
TSSOP (y)
TDfn (ZD2)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
funCTIOnAl SyMbOl
VCC
SCL
A2, A1, A0
WP
CAT24C256
SDA
For the location of Pin , please consult the
corresponding package drawing.
PIn funCTIOnS
A
0
, A
, A
2
SDA
SCL
WP
V
CC
V
SS
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
VSS
* Catalyst carries the I
2
C protocol under a license from the Philips Corporation.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-04, Rev. F
CAT24C256
AbSOluTE MAXIMuM RATIngS
(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
RElIAbIlITy CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
,000,000
00
units
Program/ Erase Cycles
Years
-65°C to +50°C
-0.5 V to +6.5 V
D.C. OPERATIng CHARACTERISTICS
V
CC
= .8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
I
CC
I
SB
I
L
V
IL
V
IH
V
OL
V
OL2
Parameter
Supply Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
≥ 2.5 V, I
OL
= 3.0mA
V
CC
< 2.5 V, I
OL
= .0mA
Test Conditions
Read or Write at 400kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
-0.5
Min
Max
V
CC
x 0.3
0.4
0.2
V
CC
x 0.7 V
CC
+ 0.5
units
mA
µA
µA
V
V
V
V
PIn IMPEDAnCE CHARACTERISTICS
V
CC
= .8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
C
IN(3)
C
IN(3)
I
WP(5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
(CAT24C256 Rev. C - New Product)
Conditions
V
IN
= 0V
V
IN
= 0V
V
IN
< V
IH,
V
CC
= 5.5V
V
IN
< V
IH,
V
CC
= 3.3V
V
IN
< V
IH,
V
CC
= .8V
V
IN
> V
IH
notes:
() Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+ 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -.5V or overshoot to no more than V
CC
+ .5V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q00
and JEDEC test methods.
(4) Page Mode, V
CC
= 5V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
The variable WP input impedance is available only for Die Rev. C, New Product.
Doc. No. MD-04, Rev. F
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Min
Max
8
6
200
50
00
units
pF
pF
µA
2
CAT24C256
A.C. CHARACTERISTICS
(1)
V
CC
= .8 V to 5.5 V, T
A
= -40°C to 85°C,
unless otherwise specified.
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(2)
t
F(2)
t
SU:STO
t
BUF
t
AA
t
DH
T
i(2)
t
SU:WP
t
HD:WP
t
WR
t
PU(2, 3)
notes:
() Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
fast
Min
0.6
.3
0.6
0.6
0
00
Max
400
units
kHz
µs
µs
µs
µs
µs
ns
300
300
0.6
.3
ns
ns
µs
µs
0.9
00
00
0
2.5
µs
ns
ns
µs
µs
5
ms
ms
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
Min
4
4.7
4
4.7
0
250
Max
00
000
300
4
4.7
3.5
00
00
0
2.5
5
A.C. TEST COnDITIOnS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V
CC
to 0.8 x V
CC
≤
50ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
OL
= 3mA (V
CC
≥
2.5V); I
OL
= mA (V
CC
< 2.5V); C
L
= 00pF
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. MD-04, Rev. F
CAT24C256
POWER-On RESET (POR)
The CAT24C256 Die Rev. C incorporates Power-On
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state.
The device will power up into Standby mode after V
CC
exceeds the POR trigger level and will power down
into Reset mode when V
CC
drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a tem-
porary loss of power.
I
2
C buS PROTOCOl
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure ).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake-up’ call to all receivers. Absent
a START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP starts the internal Write cycle (when follow-
ing a Write command) or sends the Slave into standby
mode (when following a Read command).
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address are set to 00, for normal Read/Write opera-
tions (Figure 2). The next 3 bits, A
2
, A
and A
0
, select
one of 8 possible Slave devices. The last bit, R/W,
specifies whether a Read (1) or Write (0) operation is
to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
th
clock cycle (Figure 3). The Slave will
also acknowledge the byte address and every data
byte presented in Write mode. In Read mode the Slave
shifts out a data byte, and then releases the SDA line
during the 9
th
clock cycle. If the Master acknowledges
the data, then the Slave continues transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by sending a STOP to
the Slave. Bus timing is illustrated in Figure 4.
PIn DESCRIPTIOn
SCl:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A
0
, A
1
and A
2
:
The Address pins accept the device ad-
dress. These pins have on-chip pull-down resistors.
WP:
The Write Protect input pin inhibits all write op-
erations, when pulled HIGH. This pin has an on-chip
pull-down resistor.
funCTIOnAl DESCRIPTIOn
The CAT24C256 supports the Inter-Integrated Circuit
(I
2
C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C256
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver. Up to 8 devices may be
connected to the bus as determined by the device ad-
dress inputs A
0
, A
, and A
2
.
Doc. No. MD-04, Rev. F
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C256
figure 1. Start/Stop Timing
SCL
SDA
START
CONDITION
STOP
CONDITION
figure 2. Slave Address bits
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
ACK SETUP (≥ tSU:DAT)
figure 4. bus Timing
tF
tLOW
SCL
tSU:STA
SDA IN
tAA
SDA OUT
tDH
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. MD-04, Rev. F
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