74AC373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74AC373B
74AC373M
DESCRIPTION
The 74AC373 is a high-speed CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology.
These 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched at the
PIN CONNECTION AND IEC LOGIC SYMBOLS
O
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
logic level of D input data. While the (OE) input is
low, the 8 outputs will be in a normal logic state
(high or low logic level); while OE is in high level
the outputs will be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
P
te
le
od
r
s)
t(
uc
T&R
74AC373MTR
74AC373TTR
April 2001
1/11
74AC373
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
400
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
T
stg
Storage Temperature
T
L
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time V
CC
= 3.0, 4.5 or 5.5V (note 1)
Parameter
Value
2 to 6
0 to V
CC
1) V
IN
from 30% to 70% of V
CC
O
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
te
le
r
P
0 to V
CC
8
-55 to 125
od
s)
t(
uc
Unit
V
V
V
°C
ns/V
3/11
74AC373
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
5.0
(**)
T
A
= 25°C
Min.
Typ.
6.5
5.0
6.5
5.0
7.0
5.0
7.5
6.5
1.5
1.5
0.5
0.5
-0.5
-0.5
Max.
12.0
9.5
12.0
9.5
11.0
8.5
12.0
9.0
5.5
4.0
5.5
4.0
Value
-40 to 85°C
Min.
Max.
14.0
10.5
14.0
10.5
13.0
9.5
13.0
10.0
6.0
4.5
6.0
-55 to 125°C
Min.
Max.
14.0
10.5
14.0
10.5
13.0
9.5
13.0
10.0
6.0
ns
ns
Unit
t
PLH
t
PHL
Propagation Delay
Time
LE to Q
t
PLH
t
PHL
Propagation Delay
Time
D to Q
t
PZL
t
PZH
Output Enable
Time
t
PLZ
t
PHZ
Output Disable
Time
t
W
CLOCK Pulse
Width HIGH or
LOW
Setup Time D to
CLOCK, HIGH or
LOW
Hold Time D to
CLOCK, HIGH or
LOW
ns
ns
t
s
t
h
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
5.0
5.0
5.0
C
IN
C
OUT
C
PD
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance (note
1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/n (per circuit)
O
so
b
te
le
ro
P
uc
d
s)
t(
so
b
-O
Min.
4
8
20
P
te
le
1.0
Value
Max.
Min.
1.0
od
r
4.5
5.0
5.0
ct
u
4.5
6.0
4.5
s)
(
ns
ns
5.0
5.0
ns
T
A
= 25°C
Typ.
-40 to 85°C
Max.
-55 to 125°C
Min.
Max.
Unit
pF
pF
pF
f
IN
= 10MHz
5/11
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