IRFR120, IRFU120
Data Sheet
January 2002
8.4A, 100V, 0.270 Ohm, N-Channel
Power MOSFETs
These are N-Channel enhancement mode silicon gate
power field effect transistors. They are advanced power
MOSFETs designed, tested, and guaranteed to withstand a
specified level of energy in the breakdown avalanche mode
of operation. All of these power MOSFETs are designed for
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
power bipolar switching transistors requiring high speed and
low gate drive power. These types can be operated directly
from integrated circuits.
Formerly developmental type TA09594.
Features
• 8.4A, 100V
• r
DS(ON)
= 0.270Ω
• Single Pulse Avalanche Energy Rated
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
IRFR120
IRFU120
PACKAGE
TO-252AA
TO-251AA
BRAND
IFR120
IFU120
Symbol
D
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in the tape and reel, i.e., IRFR120T.
S
Packaging
JEDEC TO-251AA
SOURCE
DRAIN
GATE
GATE
JEDEC TO-252AA
DRAIN
(FLANGE)
DRAIN
DRAIN (FLANGE)
SOURCE
©2002 Fairchild Semiconductor Corporation
IRFR120, IRFU120 Rev. B
IRFR120, IRFU120
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
IRFR120, IRFU120
100
100
8.4
5.9
34
±20
50
0.33
36
-55 to 175
300
260
UNITS
V
V
A
A
A
V
W
W/
o
C
mJ
o
C
o
C
o
C
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulse Avalanche Energy Rating (Figure 14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J,
T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
I
DSS
I
D(ON)
I
GSS
r
DS(ON)
g
fs
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(TOT)
Q
gs
Q
gd
C
ISS
C
OSS
C
RSS
L
D
Measured from the Drain
Lead, 6.0mm (0.25in) from
Package to Center of Die
Measured from the Source
Lead, 6.0mm (0.25in) from
Package to Source
Bonding Pad
Modified MOSFET
Symbol Showing the
Internal Device
Inductances
D
L
D
G
L
S
S
TEST CONDITIONS
I
D
= 250µA, V
GS
= 0V (Figure 10)
V
GS
= V
DS
, I
D
= 250µA
V
DS
= Rated BV
DSS
, V
GS
= 0V
V
DS
= 0.8 x Rated BV
DSS
, V
GS
= 0V, T
J
= 150
o
C
V
DS
> I
D(ON)
x r
DS(ON)MAX
, V
GS
= 10V
V
GS
=
±20V
I
D
= 5.9A, V
GS
= 10V (Figures 8, 9)
V
DS
≥
50V, I
D
= 5.9A (Figure 12)
V
DD
=
50V, I
D
≅
8.4A, R
GS
= 18Ω, R
L
= 5.1Ω
MOSFET Switching Times are Essentially
Independent of Operating Temperature
MIN
100
2.0
-
-
8.4
-
-
2.8
-
-
-
-
TYP
-
-
-
-
-
-
0.25
4.2
8.8
30
19
20
9.7
2.2
2.3
350
130
24
4.5
MAX
-
4.0
25
250
-
±500
0.27
-
13
45
29
30
15
3.3
3.4
-
-
-
-
UNITS
V
V
µA
µA
A
nA
Ω
S
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
nH
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
On-State Drain Current (Note 2)
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Forward Transconductance (Note 2)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
(Gate to Source + Gate to Drain)
Gate to Source Charge
Gate to Drain “Miller” Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Internal Drain Inductance
V
GS
= 10V, I
D
= 8.4A, V
DS
= 0.8 x Rated BV
DSS
,
I
G(REF)
= 1.5mA (Figure 14) Gate Charge is
Essentially Independent of Operating Temperature
-
-
-
V
DS
= 25V, V
GS
= 0V, f = 1MHz (Figure 11)
-
-
-
-
Internal Source Inductance
L
S
-
7.5
-
nH
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
R
θJC
R
θJA
Typical Solder Mount
-
-
-
-
3.0
110
o
C/W
o
C/W
©2002 Fairchild Semiconductor Corporation
IRFR120, IRFU120 Rev. B
IRFR120, IRFU120
Source to Drain Diode Specifications
PARAMETER
Continuous Source to Drain Current
Pulse Source to Drain Current (Note 3)
SYMBOL
I
SD
I
SDM
TEST CONDITIONS
Modified MOSFET
Symbol Showing the
Integral Reverse P-N
Junction Rectifier
G
D
MIN
-
-
TYP
-
-
MAX
8.4
34
UNITS
A
A
Source to Drain Diode Voltage (Note 2)
Reverse Recovery Time
Reverse Recovery Charge
NOTES:
V
SD
t
rr
Q
RR
S
o
C, I
T
J
= 25
SD
= 8.4A, V
GS
= 0V (Figure 13)
T
J
= 25
o
C, I
SD
= 8.4A, dI
SD
/dt = 100A/µs
T
J
= 25
o
C, I
SD
= 8.4A, dI
SD
/dt = 100A/µs
-
55
0.25
-
110
0.53
2.5
240
1.1
V
ns
µC
2. Pulse test: pulse width
≤
300µs, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. V
DD
= 25V, starting T
J
= 25
o
C, L = 770µH, R
G
= 25Ω, Peak I
AS
= 8.4A.
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
Unless Otherwise Specified
10
I
D
, DRAIN CURRENT (A)
8
6
4
2
0
0
25
0
50
75
100
T
C
, CASE TEMPERATURE (
o
C)
125
150
175
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
10
Z
θJC
, THERMAL IMPEDANCE
0.5
1
0.2
0.1
0.05
0.1
0.02
0.01
SINGLE PULSE
P
DM
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
+ T
C
0.1
10
-3
10
-2
t
1
, RECTANGULAR PULSE DURATION (s)
1
10
10
-2
10
-5
10
-4
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2002 Fairchild Semiconductor Corporation
IRFR120, IRFU120 Rev. B
IRFR120, IRFU120
Typical Performance Curves
100
10µs
I
D
, DRAIN CURRENT (A)
100µs
10
1ms
10ms
I
D
, DRAIN CURRENT (A)
Unless Otherwise Specified
(Continued)
15
V
GS
= 10V
V
GS
= 8V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
GS
= 7V
12
9
V
GS
= 6V
6
V
GS
= 5V
V
GS
= 4V
0
1
OPERATION IN THIS
AREA IS LIMITED
BY r
DS(ON)
T
J
= MAX RATED
T
C
= 25
o
C
SINGLE PULSE
DC
3
0.1
1
10
100
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1000
0
10
20
30
40
50
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. OUTPUT CHARACTERISTICS
15
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
I
D
, DRAIN CURRENT (A)
12
I
DS(ON)
, ON STATE DRAIN CURRENT (A)
V
GS
= 10V
V
GS
= 8.0V
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DS
≥
50V
V
GS
= 7.0V
9
V
GS
= 6.0V
6
V
GS
= 5.0V
V
GS
= 4.0V
0
0
1
2
3
4
5
10
1
T
J
= 175
o
C
T
J
= 25
o
C
3
0.1
0
2
4
6
8
V
GS
, GATE TO SOURCE VOLTAGE (V)
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 6. SATURATION CHARACTERISTICS
FIGURE 7. TRANSFER CHARACTERISTICS
2.5
r
DS(ON)
, ON-STATE RESISTANCE (S)
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
3.0
2.0
V
GS
= 10V
1.5
2.4
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
GS
= 10V, I
D
= 5.9A
1.8
1.0
V
GS
= 20V
0.5
1.2
0.6
0
0
0
8
16
24
I
D
, DRAIN CURRENT (A)
32
40
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
IRFR120, IRFU120 Rev. B
IRFR120, IRFU120
Typical Performance Curves
1.25
I
D
= 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.15
Unless Otherwise Specified
(Continued)
1000
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
800 C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GD
600
1.05
0.95
C, CAPACITANCE (pF)
400
C
ISS
C
OSS
C
RSS
0.85
200
0.75
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
0
1
2
5
10
2
5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
5
g
fs
, TRANSCONDUCTANCE (S)
4
T
J
= 25
o
C
I
SD
, SOURCE TO DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DS
≥
50V
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
10
3
T
J
= 175
o
C
2
1
T
J
= 175
o
C
T
J
= 25
o
C
1
0
0.1
0
3
6
9
I
D
, DRAIN CURRENT (A)
12
15
0
0.4
0.8
1.2
1.6
V
SD
, SOURCE TO DRAIN VOLTAGE (V)
2.0
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT
FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
I
D
= 8.4A
V
GS
, GATE TO SOURCE (V)
16
V
DS
= 80V
V
DS
= 50V
V
DS
= 20V
12
8
4
0
0
3
6
9
12
15
Q
g
, GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
©2002 Fairchild Semiconductor Corporation
IRFR120, IRFU120 Rev. B
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