PRELIMINARY
‡
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
FLASH MEMORY
MT28F322P3
Low Voltage, Extended Temperature
FEATURES
• Flexible dual-bank architecture
Support for true concurrent operation with zero
latency
Read bank
a
during program bank
b
and vice
versa
Read bank
a
during erase bank
b
and vice versa
• Basic configuration:
Seventy-one erasable blocks
Bank
a
(8Mb for data storage)
Bank
b
(24Mb for program storage)
• V
CC
, V
CC
Q, V
PP
voltages
2.7V (MIN), 3.3V (MAX) V
CC
2.2V (MIN), 3.3V (MAX) V
CC
Q
3.0V (TYP) V
PP
(in-system PROGRAM/ERASE)
12V ±5% (HV) V
PP
tolerant (factory programming
compatibility)
• Random access time: 70ns @ 2.7V V
CC
• Page Mode read access
Eight-word page
Interpage read access: 70ns @ 2.7V
Intrapage read access: 30ns @ 2.7V
• Low power consumption (V
CC
= 3.3V)
Asynchronous/interpage READ < 15mA
Intrapage READ < 7mA
WRITE < 20mA (MAX)
ERASE < 25mA (MAX)
Standby < 15µA (TYP), 50µA (MAX) @ 3.3V
Automatic power save (APS) feature
• Enhanced write and erase suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Dual 64-bit chip protection registers for security
purposes
• Cross-compatible command support
Extended command set
Common flash interface
• PROGRAM/ERASE cycle
100,000 WRITE/ERASE cycles per block
• Fast programming algorithm
V
PP
= 12V ±5%
BALL ASSIGNMENT
48-Ball FBGA
1
A
B
C
D
E
F
A13
2
A11
3
A8
4
V
PP
5
WP#
6
A19
7
A7
8
A4
A14
A10
WE#
RST#
A18
A17
A5
A2
A15
A12
A9
NC
A20
A6
A3
A1
A16
DQ14
DQ5
DQ11
DQ2
DQ8
CE#
A0
V
CC
Q
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
V
SS
V
SS
DQ7
DQ13
DQ4
V
CC
DQ10
DQ1
OE#
Top View
(Ball Down)
NOTE:
See page 7 for Ball Description Table.
See page 35 for mechanical drawing.
OPTIONS
• Timing
70ns access
80ns access
• Boot Block Configuration
Top
Bottom
• Package
48-ball FBGA (6 x 8 ball grid)
• Operating Temperature Range
Commercial (0ºC to +70ºC)
Extended (-40ºC to +85ºC)
Part Number Example:
MARKING
-70
-80
T
B
FJ
None
ET
MT28F322P3FJ-70 BET
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
1
©2002, Micron Technology, Inc.
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR
EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
GENERAL DESCRIPTION
The MT28F322P3 is a high-performance, high-
density, nonvolatile memory solution that can
significantly improve system performance. This new
architecture features a two-memory-bank configura-
tion that supports background operation with no
latency.
A high-performance bus interface allows a fast page
mode data transfer; a conventional asynchronous bus
interface is provided as well.
The MT28F322P3 allows soft protection for blocks,
as read only, by configuring soft protection registers
with dedicated command sequences. For security pur-
poses, two 64-bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). Two on-chip status registers, one for
each of the two memory partitions, can be used to moni-
tor the WSM status and to determine the progress of
the program/erase task.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation soft-
ware packages.
The device is manufactured using 0.18µm process
technology.
Please refer to Micron’s Web site (www.micron.com/
flash)
for the latest data sheet.
ARCHITECTURE AND MEMORY
ORGANIZATION
The MT28F322P3 Flash device contains two sepa-
rate banks of memory (bank
a
and bank
b)
for simulta-
neous READ and WRITE operations.
The MT28F322P3 Flash memory is available in the
following bank segmentation configuration:
• Bank
a
comprises one-fourth of the memory
and contains 8 x 4K-word parameter blocks
and 15 x 32K-word blocks.
• Bank
b
represents three-fourths of the
memory, is equally sectored, and contains
48 x 32K-word blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part num-
bers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28F322P3FJ-70 BET
MT28F322P3FJ-70 TET
MT28F322P3FJ-80 BET
MT28F322P3FJ-80 TET
PRODUCT
MARKING
FW816
FW817
FW814
FW815
SAMPLE
MARKING
FX816
FX817
FX814
FX815
MECHANICAL
SAMPLE MARKING
FY816
FY817
FY814
FY815
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
PART NUMBERING INFORMATION
Micron’s low-power devices are available with sev-
eral different combinations of features (see Figure 1).
Valid combinations of features and their correspond-
ing part numbers are listed in Table 2.
Figure 1
Part Number Chart
MT 28F 322 P 3 FJ -70 T ET
Micron Technology
Flash Family
28F = Dual-Supply Flash
Operating Temperature Range
None = Commercial (0ºC to +70ºC)
ET = Extended (-40ºC to +85ºC)
Boot Block Starting Address
B = Bottom boot
T = Top boot
Density/Organization/Banks
322 = 32Mb (2,048K x 16)
bank
a
= 1/4; bank
b
= 3/4
Access Time
-70 = 70ns
-80 = 80ns
Read Mode Operation
P = Asynchronous/Page Read
Package Code
Operating Voltage Range
3 = 2.7V–3.3V
FJ = 48-ball FBGA (6 x 8 grid)
Table 2
Valid Part Number Combinations
ACCESS
TIME (ns)
70
70
80
80
BOOT BLOCK
STARTING
ADDRESS
Bottom
Top
Bottom
Top
OPERATING
TEMPERATURE
RANGE
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
PART NUMBER
MT28F322P3FJ-70 BET
MT28F322P3FJ-70 TET
MT28F322P3FJ-80 BET
MT28F322P3FJ-80 TET
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
PR Lock
PR Lock
Query
Query/OTP
OTP
DQ0–DQ15
X DEC
Data Input
Buffer
Data
Register
RST#
CE#
WE#
OE#
Y/Z DEC
Bank 1 Blocks
Y/Z Gating/Sensing
Manufacturer’s ID
Device ID
Block Lock
RCR
ID Reg.
CSM
Status
Reg.
WSM
Program/
Erase
Pump Voltage
Generators
Output
Multiplexer
DQ0–DQ15
I/O Logic
Output
Buffer
A0–A20
Address
Input
Buffer
Address
CNT WSM
Address
Multiplexer
Y/Z DEC
X DEC
Y/Z Gating/Sensing
Bank 2 Blocks
Address Latch
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
Figure 2
Bottom Boot Block Device
Block
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Bank
b
= 24Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Address Range
(x16)
1F8000h-1FFFFFh
1F0000h-1F7FFFh
1E8000h-1EFFFFh
1E0000h-1E7FFFh
1D8000h-1DFFFFh
1D0000h-1D7FFFh
1C8000h-1CFFFFh
1C0000h-1C7FFFh
1B8000h-1BFFFFh
1B0000h-1B7FFFh
1A8000h-1AFFFFh
1A0000h-1A7FFFh
198000h-19FFFFh
190000h-197FFFh
188000h-18FFFFh
180000h-187FFFh
178000h-17FFFFh
170000h-177FFFh
168000h-16FFFFh
160000h-167FFFh
158000h-15FFFFh
150000h-157FFFh
148000h-14FFFFh
140000h-147FFFh
138000h-13FFFFh
130000h-137FFFh
128000h-12FFFFh
120000h-127FFFh
118000h-11FFFFh
110000h-117FFFh
108000h-10FFFFh
100000h-107FFFh
0F8000h-0FFFFFh
0F0000h-0F7FFFh
0E8000h-0EFFFFh
0E0000h-0E7FFFh
0D8000h-0DFFFFh
0D0000h-0D7FFFh
0C8000h-0CFFFFh
0C0000h-0C7FFFh
0B8000h-0BFFFFh
0B0000h-0B7FFFh
0A8000h-0AFFFFh
0A0000h-0A7FFFh
098000h-097FFFh
090000h-097FFFh
088000h-087FFFh
080000h-087FFFh
Block
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bank
a
= 8Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Address Range
(x16)
078000h-07FFFFh
070000h-077FFFh
068000h-067FFFh
060000h-067FFFh
058000h-05FFFFh
050000h-057FFFh
048000h-04FFFFh
040000h-047FFFh
038000h-03FFFFh
030000h-037FFFh
028000h-02FFFFh
020000h-027FFFh
018000h-01FFFFh
010000h-017FFFh
008000h-00FFFFh
007000h-007FFFh
006000h-006FFFh
005000h-005FFFh
004000h-004FFFh
003000h-003FFFh
002000h-002FFFh
001000h-001FFFh
000000h-000FFFh
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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