A43L1632A
Preliminary
Features
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks / Pulse
RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM for masking
Clock Frequency (max) : 166MHz @ CL=3 (-6)
143MHz @ CL=3 (-7)
512K X 32 Bit X 4 Banks Synchronous DRAM
Auto & self refresh
64ms refresh period (4K cycle)
86 Pin TSOP (II)
Commercial operating temperature range: 0ºC to + 70º
C
Industrial operating temperature range: -40ºC to +85ºC
for -U series
Available in 90 Balls CSP (8mm X 13mm)
Package is available to lead free (-F series)
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A43L1632A is 67,108,864 bits Low Power
synchronous high data rate Dynamic RAM organized as 2
X 1,048,576 words by 32 bits, fabricated with AMIC’s high
performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
Pin Configuration
90 Balls CSP (8 mm x 13 mm)
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ
26
DQ
28
VSSQ
VSSQ
VDDQ
VSS
A4
A7
CLK
DQM
1
VDDQ
VSSQ
VSSQ
DQ
11
DQ
13
90 Ball (8X13) CSP
2
3
7
DQ
24
VDDQ
DQ
27
DQ
29
DQ
31
DQM
3
A5
A8
CKE
NC
DQ
8
DQ
10
DQ
12
VDDQ
DQ
15
VSS
VSSQ
DQ
25
DQ
30
NC
A3
A6
NC
A9
NC
VSS
DQ
9
DQ
14
VSSQ
VSS
VDD
VDDQ
DQ
22
DQ
17
NC
A2
8
DQ
23
VSSQ
DQ
20
DQ
18
DQ
16
DQM
2
A0
BA1
CS
9
DQ
21
DQ
19
VDDQ
VDDQ
VSSQ
VDD
A1
A10
NC
BA0
CAS
NC
RAS
WE
DQM
0
VSSQ
VDDQ
VDDQ
DQ
4
DQ
2
VDD
DQ
6
DQ
1
VDDQ
VDD
DQ
7
DQ
5
DQ
3
VSSQ
DQ
0
PRELIMINARY
(February, 2008, Version 0.1)
1
AMIC Technology, Corp.
A43L1632A
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except CLK,
CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A10
Address
Row address : RA0~RA10, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
BA0, BA1
Bank Select Address
Selects band for read/write during column address latch time.
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Column Address
Strobe
Latches column addresses on the positive going edge of the CLK with
CAS
low.
Enables column access.
RAS
CAS
WE
DQM
0-3
DQ
0-31
VDD/VSS
VDDQ/VSSQ
NC/RFU
Write Enable
Data Input/Output
Mask
Data Input/Output
Power
Supply/Ground
Data Output
Power/Ground
No Connection
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when DQM
0-3
active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V
±
0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
PRELIMINARY
(February, 2008, Version 0.1)
4
AMIC Technology, Corp.
FPGA/CPLD
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