PRELIMINARY
PD 9.1091A
IRL2203S
HEXFET
®
Power MOSFET
l
Logic-Level Gate Drive
l
Surface Mount
l
Advanced Process Technology
l
Dynamic dv/dt Rating
l
175°C Operating Temperature
l
Fast Switching
l
Fully Avalanche Rated
Description
D
V
DSS
= 30V
R
DS(on)
= 0.007Ω
G
I
D
= 100A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
D
2
Pak
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
A
= 25°C
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
100
71
400
3.8
130
0.83
± 20
390
60
13
1.2
-55 to + 175
300 (1.6mm from case )
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
–––
–––
Max.
1.2
40
Units
°C/W
IRL2203S
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Min.
30
–––
–––
–––
1.0
47
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.035
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
15
210
29
54
Max. Units
Conditions
–––
V
V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 1mA
0.007
V
GS
= 10V, I
D
= 60A
0.01
V
GS
= 4.5V, I
D
= 50A
2.5
V
V
DS
= V
GS
, I
D
= 250µA
–––
S
V
DS
= 25V, I
D
= 60A
25
V
DS
= 30V, V
GS
= 0V
µA
250
V
DS
= 24V, V
GS
= 0V, T
J
= 150°C
100
V
GS
= 20V
nA
-100
V
GS
= -20V
110
I
D
= 60A
31
nC V
DS
= 24V
57
V
GS
= 4.5V, See Fig. 6 and 13
–––
V
DD
= 15V
–––
I
D
= 60A
ns
–––
R
G
= 1.8Ω, V
GS
= 4.5V
–––
R
D
= 0.25Ω, See Fig. 10
Between lead,
7.5
nH
–––
and center of die contact
3500 –––
V
GS
= 0V
1400 –––
pF
V
DS
= 25V
690 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
Notes:
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
–––
–––
–––
––– 100
A
–––
–––
94
280
400
1.3
140
410
V
ns
nC
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
T
J
= 25°C, I
S
= 60A, V
GS
= 0V
T
J
= 25°C, I
F
= 60A
di/dt = 100A/µs
D
S
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width
≤
300µs; duty cycle
≤
2%.
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handling of the
package refer to Design Tip # 93-4
V
DD
= 15V, starting T
J
= 25°C, L = 220µH
R
G
= 25Ω, I
AS
= 60A. (See Figure 12)
I
SD
≤
60A, di/dt
≤
140A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C
Uses IRL2203N data and test conditions.
** When mounted on FR-4 board using minimum recommended footprint.
For recommended footprint and soldering techniques refer to application note #AN-994.
IRL2203S
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
1000
I
D
, D ra in -to -S o u rce C u rre n t (A )
I
D
, D ra in -to -S o u rce C u rre n t (A )
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
100
100
10
10
2 .5V
2.5 V
2 0µ s PU L SE W ID TH
T
J
= 2 5°C
0.1
1
10
1
A
1
0.1
1
2 0µ s PU L SE W ID TH
T
J
= 1 75 °C
10
A
100
100
V
D S
, Drain-to-S ource Voltage (V )
V
D S
, Drain-to-S ource Voltage (V )
Fig 1.
Typical Output Characteristics,
T
J
= 25
o
C
Fig 2.
Typical Output Characteristics,
T
J
= 175
o
C
1000
2.0
T
J
= 2 5 °C
100
R
DS (on )
, Drain-to-S ource O n Resistance
( Norm alized)
I
D
= 100 A
I
D
, D r ain- to-S ourc e C urre nt (A )
1.5
T
J
= 1 75 °C
1.0
10
0.5
1
2.0
3.0
4.0
5.0
V
DS
= 1 5 V
2 0 µ s P U L SE W ID TH
6.0
7.0
8.0
9.0
A
0.0
-60 -40 -20
0
20
40
60
80
V
G S
= 10V
A
100 120 140 160 180
V
G S
, Ga te-to-S o urce V oltage (V )
T
J
, Junction Tem perature (°C )
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
IRL2203S
8000
C , C a p a c ita n c e (p F )
6000
C
is s
C
os s
V
G S
, Gate-to-Source Voltage ( V)
V
GS
C
is s
C
rs s
C
o ss
= 0 V,
f = 1M H z
= C
gs
+ C
gd
, C
ds
SH O RTE D
= C
gd
= C
ds
+ C
g d
15
I
D
= 60A
V
D S
= 24 V
V
D S
= 15 V
12
9
4000
6
C
rs s
2000
3
0
1
10
100
A
0
0
30
60
FOR TE ST CIR C UIT
SEE FIGU RE 1 3
A
90
120
150
V
D S
, Drain-to-Source V oltage (V)
Q
G
, T otal G ate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
I
S D
, R e v e rse D ra in C u rre n t (A )
O PER ATIO N IN TH IS AR EA L IM ITED
BY R
DS (o n)
10 µs
T
J
= 25 °C
T
J
= 17 5°C
100
I
D
, D ra in C u rre n t (A )
100
10 0µs
1m s
10
10m s
10
0.5
1.0
1.5
2.0
2.5
V
G S
= 0 V
3.0
A
1
1
T
C
= 25 °C
T
J
= 17 5°C
S ing le Pulse
10
100
A
3.5
V
S D
, S ource-to-Drain Voltage (V )
V
D S
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
IRL2203S
V
DS
100
R
D
L IM ITED BY PAC KA GE
V
GS
R
G
D.U.T.
+
80
I
D
, D ra in C u rre n t (A m p s)
-
V
DD
5.0V
60
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
40
Fig 10a.
Switching Time Test Circuit
V
DS
20
90%
0
25
50
75
100
125
150
A
175
T
C
, C ase T em perature (°C )
10%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 9.
Maximum Drain Current Vs.
Case Temperature
10
Fig 10b.
Switching Time Waveforms
T her m al R e spon se ( Z
th J C
)
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
S INGLE PULS E
( THER MAL R ESP ONS E)
0.01
0.00001
0.0001
0.001
0.01
P
DM
t
1
t
2
Notes :
1. D uty fac tor D = t
1
/ t
2
2. P ea k TJ = P D M x Z thJ C + T C
A
10
0.1
1
t
1
, R ectan gular P ulse D u ration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
