Four Port Switched Fast Ethernet
Controller
FEATURES
• Single-chip 4-port Switched Fast Ethernet Controller
- Provides packet switching functions between four
on-chip Fast Ethernet ports and the PCI bus
- Switch expansion via 66MHz PCI bus (2Gbps)
- Designed for Fast Ethernet Switches from 4 ports
to 24 ports
• GalNet® Architecture Family Member
- Connects to other GalNet Family Devices through
33MHz-to-66MHz PCI bridges
- 100% software compatible with GT-48002A
• Incorporates four 802.3 compliant 10/100Mbps Media
Access Controllers
- Direct Interface to MII (Media Independent
Interface)
- Half/Full Duplex Support (up to 200 Mbps/port)
- IEEE 802.3 100Base-TX, T4, and FX compatible
• Full MII Management Support (MDC/MDIO) via CPU
• Auto-negotiation supported through MII Interface
• Direct support for packet buffering
- Glueless interface to 2 or 4 Mbyte of 35ns EDO
DRAM
- Up to 2K buffers, 1536-bytes each, dynamically
• High-Performance Distributed Switching Engine
- Performs forwarding and filtering at full wire speed
- 148,800 packets/s on each Ethernet port
- Flexible software or hardware intervention in
packet routing decisions
- allocated to the receive and PCI ports
• Virtual LAN Support
- Port based virtual LANs
- Ability to define “super-VLANs” that span multiple
VLANs
• Quality-of-Service Queuing
- Priority queuing based on port number or MAC
address
GT-48004A
Preliminary
Revision 1.0
2/13/98
Please contact Galileo Technology for possible
updates before finalizing a design.
• Advanced address recognition
- Intelligent address recognition mechanism enables
forwarding rate at full wire speed
- Self-learning mechanism
- Supports up to 8K Unicast addresses and
unlimited Multicast/Broadcast addresses
- Broadcast storm filtering
• 66MHz Fast PCI interface for switch expansion and
management CPU connection
- Up to 6 GT-48004A devices per PCI bus segment
without PCI-to-PCI bridging (24 ports)
- Up to 32 GalNet devices in a single switch
- Standard CPU connection for management (66
MHz PCI connection through GT-641xx chips)
• Extensive network management support
- Repeater MIB and PCI counters
- Address aging support
- Hardware assist for Spanning Tree algorithm
- RMON Station-to-Station connectivity matrix
- CPU access to Address Table
- Ability to define static addresses
- Monitoring (sniffer) mode
• Packet sampling management technology
- Takes “snapshots” of packets at programmable
intervals
- Allows for the implementation of RMON with low-
cost CPUs
• High observability LED interface
- Dual 3 pin serial LED interfaces give access to
over 80 internal status signals
• 329 pin BGA package
- Advanced 0.35 micron CMOS process
- 3.3V supply, 5V tolerant I/O
FAST PCI
EDO
DRAM
GT-48004A
EDO
DRAM
EDO
DRAM
GT-48004A
EDO
DRAM
EDO
DRAM
GT-48004A
EDO
DRAM
EDO
DRAM
GT-48004A
EDO
DRAM
4 x MII
4 x MII
4 x MII
MII PHY
Devices
MII PHY
Devices
MII PHY
Devices
MII PHY
Devices
4 x Fast Ethernet
4 x Fast Ethernet
4 x Fast Ethernet
4 x Fast Ethernet
www.galileoT.com
support@galileoT.com
Tel: +1-408.451.1400
Fax: +1-408.451.1404
4 x MII
GT-48004A Four Port Switched Fast Ethernet Controller
TABLE
OF
CONTENTS
1. Functional Overview
1.1 The GalNet Switching Architecture........................................................................................................
1.2 Fast Ethernet Ports................................................................................................................................
1.3 Address Recognition .............................................................................................................................
1.4 CPU Packet Routing..............................................................................................................................
1.5 Intervention Mode..................................................................................................................................
1.6 VLAN Support........................................................................................................................................
1.7 Quality-of-Service/Priority Support ........................................................................................................
1.8 Network Management Features ............................................................................................................
1.9 DRAM Interface .....................................................................................................................................
1.10 Fast PCI Interface................................................................................................................................
2. Pin Information
2.1 Logic Symbol ....................................................................................................................................... 10
2.2 Pin Functions and Assignment ............................................................................................................ 11
3. Internal Architectural Overview
3.1 Internal Block Diagram ........................................................................................................................ 16
3.2 Fast Ethernet Unit Block Diagram ....................................................................................................... 17
3.3 Packet Forwarding in the GT-48004A ................................................................................................. 17
4. Operational Overview
4.1 Enabling/Disabling the GT-48004A .....................................................................................................
4.2 Basic Operation ...................................................................................................................................
4.3 Address Learning ................................................................................................................................
4.4 Packet Buffering ..................................................................................................................................
4.5 Packet Forwarding...............................................................................................................................
4.6 The GalNet Protocol ............................................................................................................................
4.7 Terminology.........................................................................................................................................
5. MAC Address Learning Process
5.1 Address Recognition ...........................................................................................................................
5.2 Recovery Process ...............................................................................................................................
5.3 Address Aging .....................................................................................................................................
5.4 Static Addresses..................................................................................................................................
5.5 Address Recognition Failure ...............................................................................................................
6. GT-48004A Buffers and Queues
6.1 Rx Buffer Threshold Programming ...................................................................................................... 23
7. Packet Forwarding
7.1 Forwarding a Unicast Packet to a Local Port ...................................................................................... 24
7.2 Forwarding a Unicast Packet to a Port in a Different GalNet Device or FEU ...................................... 24
7.3 Forwarding a Multicast Packet ............................................................................................................ 25
7.3.1 Local Ports .............................................................................................................................. 25
7.3.2 Between GalNet Devices or FEUs.......................................................................................... 25
7.3.2.1 CPU Disabled............................................................................................................. 25
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7.3.2.2 CPU Enabled.............................................................................................................
7.4 Forwarding a Packet to the CPU Directly ...........................................................................................
7.5 Forwarding a Packet from the CPU to a GalNet Device .....................................................................
7.6 CRC Generation .................................................................................................................................
7.7 Tx Watchdog Timer.............................................................................................................................
8. Device Table Operation
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8.1 Automatic Device Table Initialization .................................................................................................. 30
8.2 Manual Device Table Initialization ...................................................................................................... 30
8.3 Programming Device Numbers ........................................................................................................... 30
9. Unicast Intervention Mode
9.1 Unicast Intervention Mode Address Space ......................................................................................... 32
10. Address Table
11. GalNet Messaging Protocol
11.1 GalNet Protocol Region ....................................................................................................................
11.2 GalNet Messages Between Devices.................................................................................................
11.2.1 NEW_ADDRESS Message between GalNet devices ..........................................................
11.2.2 BUFFER_REQUEST Message between GalNet devices ....................................................
11.2.3 START_OF_PACKET Message between GalNet devices...................................................
11.2.4 PACKET_TRANSFER Message between GalNet devices ..................................................
11.2.5 END_OF_PACKET Message between GalNet devices.......................................................
11.3 GalNet Messages Between a GalNet Device and a CPU.................................................................
11.3.1 NEW_ADDRESS Message (GalNet to CPU).......................................................................
11.3.2 NEW_ADDRESS Message (CPU to GalNet).......................................................................
11.3.3 BUFFER_REQUEST Message (GalNet to CPU).................................................................
11.3.4 BUFFER_REQUEST Message (CPU to GalNet).................................................................
11.3.5 START_OF_PACKET Message (GalNet to CPU) ...............................................................
11.3.6 START_OF_PACKET Message (CPU to GalNet) ...............................................................
11.3.7 PACKET_TRANSFER Message (GalNet to CPU 16 Block Buffer) .....................................
11.3.8 PACKET_TRANSFER Message (GalNet to CPU in Unicast Intervention Mode) ................
11.3.9 PACKET_TRANSFER Message (CPU to GalNet)...............................................................
11.3.10 END_OF_PACKET Message (GalNet to CPU 16 Block Buffer) ........................................
11.3.11 END_OF_PACKET Message (GalNet to CPU in Unicast Intervention Mode) ...................
11.3.12 END_OF_PACKET Message (CPU to GalNet)..................................................................
12. Fast PCI Bus Operation
12.1 Separate Logical PCI Interfaces for Each FEU.................................................................................
12.2 Interfacing Management Processors to Fast PCI .............................................................................
12.3 PCI Configuration Header Registers.................................................................................................
12.4 Accessing DRAM and Internal Registers through the PCI Interface.................................................
12.5 Fast PCI Bandwidth/Performance Issues .........................................................................................
12.6 Plug-and-Play Considerations In PCI Systems.................................................................................
12.7 PCI Bus in Stand-Alone Systems .....................................................................................................
12.8 PCI Bus Arbiter .................................................................................................................................
13. Fast Ethernet Interfaces
13.1 10/100 MII Compatible Interface....................................................................................................... 51
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13.2 Media Access Control (MAC) ............................................................................................................
13.3 Auto-negotiation ................................................................................................................................
13.3.1 Disabled ................................................................................................................................
13.3.2 Enabled.................................................................................................................................
13.3.3 Auto-negotiation Control Per Port .........................................................................................
13.3.4 Auto-Negotiation, Software Detection...................................................................................
13.4 Backoff Algorithm Options .................................................................................................................
13.5 Data Blinder.......................................................................................................................................
13.6 Inter-Packet Gap (IPG)......................................................................................................................
13.7 10/100 Mbps MII Transmission .........................................................................................................
13.8 10/100 Mbps MII Reception...............................................................................................................
13.9 10/100 Mbps Full-Duplex Operation..................................................................................................
13.10 Illegal Frames ..................................................................................................................................
13.11 Partition Mode .................................................................................................................................
13.11.1 Enabling Partition Mode......................................................................................................
13.11.2 Entering Partition State .......................................................................................................
13.11.3 Exiting from Partition State .................................................................................................
13.12 Back-pressure .................................................................................................................................
13.13 VLAN Tagging Support....................................................................................................................
14. MII Management Interface (SMI)
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14.1 SMI Cycles ....................................................................................................................................... 57
14.1.1 SMI Timing Requirements .................................................................................................... 57
14.2 Link Detection and Link Detection Bypass (ForceLinkPass*)........................................................... 59
15. Network Management Support
15.1 Repeater MIB and PCI Counters......................................................................................................
15.2 Monitoring (Sniffer) Mode ..................................................................................................................
15.3 Spanning Tree Support .....................................................................................................................
15.4 Broadcast Storm Filtering ..................................................................................................................
16. HP-EASE Packet Sampling Technology
16.1 HP EASE Technology Overview .......................................................................................................
16.2 EASE Functionality on the GT-48004A .............................................................................................
16.3 Ease_Register ...................................................................................................................................
16.4 EASE Interrupts.................................................................................................................................
16.5 Sampled Packet Indication ................................................................................................................
16.6 Error Source Indications ....................................................................................................................
16.7 Enabling/Disabling EASE Functionality .............................................................................................
16.8 Interaction With Other GT-48004A Features.....................................................................................
17. DRAM Interface and Usage
18. LED Support
18.1 LED Indications Interface Description ............................................................................................... 68
18.2 Detailed LED Signal Description ....................................................................................................... 68
18.2.1 Primary Port Status LED....................................................................................................... 68
18.2.1.1 Primary Port Status LED in Mode 0: (LEDMode input is LOW) .............................. 68
18.2.1.2 Status LED blink timing (Mode 0)............................................................................. 68
18.2.1.3 Primary Port Status LED (Mode 1): (LEDMode input is HIGH)............................... 69
18.2.2 Transmit data in progress ..................................................................................................... 70
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18.2.3 Receive data in progress......................................................................................................
18.2.4 Collision active .....................................................................................................................
18.2.5 Full/Half duplex.....................................................................................................................
18.2.6 Receive Buffer Full ...............................................................................................................
18.2.7 Forwarding of unknown packets enabled.............................................................................
18.2.8 The port is configured as Sniffer ..........................................................................................
18.2.9 Link Fail State.......................................................................................................................
18.2.10 Partition State.....................................................................................................................
18.2.11 Secondary Port Status LED ...............................................................................................
18.2.12 Pure Port Status LED .........................................................................................................
18.3 LED Signals Timing Type .................................................................................................................
18.3.1 Static LED Signals................................................................................................................
18.3.2 Dynamic Internal Signals:.....................................................................................................
18.4 Serial LED Interface Description .......................................................................................................
18.4.1 Table of Internal Activities/Status Driven via the Serial LED Interface...............................
19. Interrupts
20. RESET Configuration
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20.1 Configuration Pins............................................................................................................................. 73
20.2 Configuration Input Timings .............................................................................................................. 73
21. Switch Expansion
22. Development Tools
22.1 Evaluation Platforms/Reference Designs ......................................................................................... 76
22.2 Verilog Models .................................................................................................................................. 76
22.3 Complimentary Products................................................................................................................... 76
23. Register Tables
23.1 Register Map.....................................................................................................................................
23.2 Internal Control Registers .................................................................................................................
23.3 Port MIB Counters (2 Blocks), Offset: 0x040000 - 0x0400ac ...........................................................
23.4 PCI Global Counters, Offset: 0x140040 - 0x140044.........................................................................
23.5 SMI Register, Offset: 0x14004c ........................................................................................................
23.6 PCI Configuration Registers .............................................................................................................
24. GT-48004A PINOUT TABLE, 329 pin BGA (sorted by ball number)
25. DC Characteristics - PRELIMINARY/SUBJECT TO CHANGE
25.1 Absolute Maximum Ratings ..............................................................................................................
25.2 Recommended Operating Conditions ...............................................................................................
25.3 DC Electrical Characteristics Over Operating Range .......................................................................
25.4 Thermal Data ....................................................................................................................................
26. AC Timing - PRELIMINARY/SUBJECT TO CHANGE
27. Functional Waveforms
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