SRAM
MT5C1009
128K x 8 SRAM
WITH CHIP & OUTPUT ENABLE
AVAILABLE AS MILITARY
SPECIFICATIONS
•SMD 5962-89598
•MIL-STD-883
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN ASSIGNMENT
(Top View)
32-Pin DIP (C, CW)
32-Pin SOJ (SOJ)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
NC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
NC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
FEATURES
•
•
•
•
•
•
•
Access Times: 12, 15, 20, 25, 35, 45, 55 and 70 ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power CMOS process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)•
Ceramic DIP (400 mil)
Ceramic DIP (600 mil)
Ceramic LCC
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
Ceramic SOJ
• 2V data retention/low power
MARKING
-12 (IT only)
-15
-20
-25
-35
-45
-55*
-70*
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
NC
WE\
A13
A8
A9
A11
OE\
A10
CE\
DQ8
DQ7
DQ6
DQ5
DQ4
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
5
6
7
8
9
10
11
12
13
A12
A14
A10
6
NC
V
CC
A15
CE2
4 3 2 1 32 31 30
NC
32-Pin Flat Pack (F)
32-Pin LCC (ECA)
29
28
27
26
25
24
23
22
21
WE
\
A13
A8
A9
A11
OE
\
A10
CE1
\
DQ8
14 15 16 17 18 19 20
GENERAL DESCRIPTION
The MT5C1009 is a 1,048,576-bit high-speed CMOS
static RAM organized as 131,072 words by 8 bits. This device
uses 8 common input and output lines and has an output en-
able pin which operate faster than address access times during
READ cycle.
For design flexibility in high-speed memory applica-
tions, this device offers chip enable (CE\) and output enable
(OE\) features. These enhancements can place the outputs in
High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is ac-
complished when WE\ remains HIGH and CE\ and OE\ go
LOW. The devices offer a reduced power standby mode when
disabled, allowing system designs to achieve low standby power
requirements.
The “L” version offers a 2V data retention mode,
reducing current consumption to 2mW maximum.
All devices operate from a single +5V power supply
and all inputs and outputs are fully TTL compatible. It is par-
ticularly well suited for use in high-density, high-speed system
applications.
C
CW
EC
ECA
F
DCJ
SOJ
L
No. 111
No. 112
No. 207
No. 208
No. 303
No. 501
No. 507
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.micross.com
MT5C1009
Rev. 6.2 01/10
Micross Components reserves the right to change products or specifications without notice.
1
DQ2
DQ3
V
SS
DQ4
DQ5
DQ6
DQ7
SRAM
MT5C1009
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
12
ROW DECODER
DQ8
I/O CONTROL
262,144-BIT
MEMORY ARRAY
DQ1
CE\
COLUMN DECODER
OE\
WE\
A
8
A
9
A
10
A
11
A
13
A
14
A
15
A
16
POWER
DOWN
NOTE:
The two least significant row address bits (A8 and A6) are encoded using gray code.
TRUTH TABLE
CE\
H
X
L
L
L
WE\
X
X
H
H
L
OE\
X
X
H
L
X
MODE
Not Selected
Not Selected
Output Disable
Read
Write
I/O PIN
High-Z
High-Z
High-Z
D
OUT
D
IN
SUPPLY CURRENT
I
SBT2
, I
SBC2
I
SBT2
, I
SBC2
I
CC
I
CC
I
CC
MT5C1009
Rev. 6.2 01/10
Micross Components reserves the right to change products or specifications without notice.
2
SRAM
MT5C1009
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range (Vcc).............................-0.5V to +6.0V
Storage Temperature......................................-65°C to +150°C
Short Circuit Output Current (per I/O)….......................20mA
Voltage on any Pin Relative to Vss..................-0.5V to +7.0V
Max Junction Temperature**.......................................+150°C
Power Dissipation ...............................................................1 W
*Stresses at or greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
will affect reliability. Refer to page 17 of this datasheet for a
technical note on this subject.
** Junction temperature depends upon package type, cycle time,
loading, ambient temperature and airflow, and humidity.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C & -45
o
C to +85
o
C; V
CC
= 5.0V +10%)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
0V<V
IN
<V
CC
Output(s) disabled
0V<V
OUT
<V
CC
I
OH
=-4.0mA
I
OL
=8.0mA
CONDITIONS
SYM
V
IH
V
IL
IL
I
IL
O
V
OH
V
OL
MIN
2.2
-0.5
-10
-10
2.4
0.4
MAX
-25
140
130
MAX
V
CC
+0.5
0.8
10
10
UNITS
V
V
μA
μA
V
V
NOTES
1
1, 2
1
1
PARAMETER
Power Supply
Current: Operating
CONDITIONS
CE\ < V
IL
; OE\ = WE\ = V
IH
,
V
CC
= MAX, f = MAX = 1/t
RC
(MIN)
Output Open
(1)
SYM
I
CCSP
I
CCLP
-12
180
180
-15
180
180
-20
140
140
-35
135
125
-45
125
115
UNITS NOTES
mA
mA
3
L version only
Power Supply
Current: Standby
CE\ > V
IH
; All Other Inputs
< V
IL
or > V
IH
, V
CC
= MAX
f = 0 Hz
CE\ > V
CC
-0.2V; V
CC
= MAX
Inputs = V
IH
or V
IL
f = 0 Hz
I
SBT
25
25
25
25
25
25
mA
I
SBCSP
I
SBCLP
10
10
10
10
10
10
10
10
10
10
10
10
mA
mA
CAPACITANCE
DESCRIPTION
Input Capacitance (A0-A16)
Output Capacitance
Input Capacitance (CE\, WE\, OE\)
MT5C1009
Rev. 6.2 01/10
CONDITIONS
T
A
= 25 C, f = 1MHz
V
CC
= 5V
o
SYM
C
I
C
O
C
I
MAX
12
20
14
UNITS
pF
pF
pF
NOTES
4
4
4
Micross Components reserves the right to change products or specifications without notice.
3
SRAM
MT5C1009
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C & -40
o
C to +85
o
C; V
CC
= 5.0V +10%)
DESCRIPTION
READ CYCLE
READ cycle time
Address access time
Chip Enable access time
Output hold from address change
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
WRITE cycle time
Chip Enable to end of write
Address valid to end of write
Address setup time
Address hold from end of write
WRITE pulse width (OE High)
Data setup time
Data hold time
Write disable to output in Low-Z
Write Enable to output in High-Z
-12
-15
-20
-25
-35
-45
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
AOE
t
LZOE
t
HZOE
t
WC
t
CW
t
AW
t
AS
t
AH
t
WP
t
DS
t
DH
t
LZWE
t
HZWE
12
11
11
0
0
11
8
0
5
7
0
7
15
12
12
0
0
12
8
0
5
7
3
3
7
7
0
7
20
12
12
0
0
12
10
0
5
9
12
12
12
3
3
7
7
0
6
25
20
20
0
0
20
15
0
5
10
15
15
15
3
3
8
6
0
10
35
25
25
0
0
25
20
0
5
15
20
20
20
3
3
10
10
0
15
45
35
35
0
0
35
20
0
5
20
25
25
25
3
3
15
15
0
20
35
35
35
3
3
20
20
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
4, 6, 7
MT5C1009
Rev. 6.2 01/10
Micross Components reserves the right to change products or specifications without notice.
4
SRAM
MT5C1009
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
480
Q
255
30 pF
Q
255
5 pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
NOTES
1.
2.
3.
All voltages referenced to V
SS
(GND).
-2V for pulse width < 20ns
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f =
1
Hz.
t
RC (MIN)
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
LZCE,
t
LZWE,
t
LZOE,
t
HZCE,
t
HZOE and
t
HZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7.
4.
5.
6.
At any given temperature and voltage condition,
t
HZCE is less than
t
LZCE, and
t
HZWE is less than
t
LZWE and
t
HZOE is less than
t
LZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
t
11. RC = Read Cycle Time.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
V
CC
for Retention Data
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
* Low Power, -20 device only
CONDITIONS
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
SYMBOL
V
DR
I
CCDR1
*
I
CCDR2
t
CDR
t
R
MIN
2
MAX
---
0.75
1.0
UNITS NOTES
V
mA
mA
ns
ns
4
4, 11
0
t
RC
---
LOW Vcc DATA RETENTION WAVEFORM
V
CC
t
CDR
DATA RETENTION MODE
4.5V
4.5V
V > 2V
DR
t
R
V
DR
CE1\
V
IH
V
IL
DON’T CARE
UNDEFINED
MT5C1009
Rev. 6.2 01/10
Micross Components reserves the right to change products or specifications without notice.
5
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