Product Specification
PE3291
Product Description
The PE3291 is a dual fractional-N FlexiPower
TM
phase-lock loop
(PLL) IC designed for frequency synthesis. Each PLL includes
a FlexiPower
TM
prescaler, phase detector, charge pump and on-
board fractional spur compensation.
The FlexiPower prescalers are supplied power on dedicated
pins and can operate at a substantial power savings at
voltages as low as 0.8 volts, while allowing a 3 volt charge
pump supply. For 3 volt only systems, on-chip voltage
regulation may be used to generate the prescaler power
supplies.
Figure 1 illustrates the implementation of the FlexiPower
technology. The prescaler power supply may be provided
externally or internally regulated down from V
DD
. In a typical
950 MHz application the total current consumed by the PLL is
2.1 mA. Operation at reduced current levels provides
significant battery life extension. The PE3291 allows the
system designer to minimize power consumption by controlling
the voltage on the prescaler. For additional operating speeds
and current consumptions refer to Figures 5 and 6.
PE3291 provides fractional-N division with power-of-two
denominator values up to 32. This allows comparison
frequencies up to 32 times the channel spacing, providing a
lower phase noise floor than integer PLLs. The 32/33 RF
prescaler (PLL1) operates up to 1200 MHz and the 16/17 IF
prescaler (PLL2) operates up to 550 MHz.
The PE3291 Phase Locked-Loop is manufactured on
Peregrine’s UltraCMOS™ process, a patented variation of
silicon-on-insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
1200 MHz / 550 MHz Dual
Fractional-N FlexiPower™ PLL
for Frequency Synthesis
Features
•
Ultra-Low Power via FlexiPower
variable supply voltages
•
Modulo-32 fractional-N main counters
•
On-board fractional spur compensation:
No tuning required, stable over
temperature
•
Improved phase noise compared to
integer-N architectures
Applications
•
CDMA handsets
•
CDMA base stations
•
Analog Cordless phones
•
One and two way pagers
Figure 1:
FlexiPower technology enables
the prescaler to operate at voltages down to
0.8 volts. This significantly reduces the total
power.
To Loop Filter
3 Volts
0.8
3 Volts
Ref.
Input
Phase Comparator
and
Charge pump
Regulator
Low
Speed Counters
Prescaler
PE3291
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
PE3291
Product Specification
Figure 2. Pin Configurations (Top View)
N/C
V
DD
CP1
GND
f
in
1
Dec1
V
DD
1
f
r
GND
1
2
3
4
5
6
7
8
9
20
V
DD
19
V
DD
18
CP2
17
GND
16
f
in
2
15
Dec2
14
V
DD
2
13
LE
12
Data
11
Clock
Figure 3. Package Type
20-lead TSSOP
f
o
LD
10
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
N/C
V
DD
CP1
GND
f
in
1
Dec1
V
DD1
f
r
GND
f
o
LD
Clock
Data
LE
V
DD2
Dec2
F
in
2
GND
CP2
V
DD
V
DD
Type
No connect.
(Note 1)
Output
Description
Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed
as close as possible to this pin and be connected directly to the ground plane.
Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external
VCO.
Ground.
Input
Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.2 GHz.
Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and
be connected directly to the ground plane.
PLL1 prescaler power supply (FlexiPower 1).
Input
Reference frequency input.
Ground.
Output
Input
Input
Input
Output
Output
Input
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and
data out of the shift register. CMOS output (see Table 11, f
o
LD Programming Truth Table).
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift
register.
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded
into one of the four appropriate latches (as assigned by the control bits).
PLL2 prescaler power supply (FlexiPower 2).
Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and
be connected directly to the ground plane.
Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz.
Ground.
Output
(Note 1)
(Note 1)
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external
VCO.
Same as pin 2.
Same as pin 2.
Note 1:
V
DD
pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
Document No. 70-0009-04
│
UltraCMOS™ RFIC Solutions
PE3291
Product Specification
PE3291 Description
The PE3291 is intended for such applications as
the local oscillator for the RF and first IF of dual-
conversion transceivers. The RF PLL (PLL1)
includes a 32/33 prescaler with a 1200 MHz
maximum frequency of operation, where the IF
PLL (PLL2) incorporates a 16/17 prescaler with a
550 MHz maximum frequency of operation. Using
an advanced fractional-N phase-locked loop
technique, the PE3291 can generate a stable,
very low phase-noise signal. The dual fractional
architecture allows fine resolution in both PLLs,
with no degradation in phase noise performance.
Data is transferred into the PE3291 via a three-
wire interface (Data, Clock, LE). Supply voltage
can range from 2.7 to 3.3 volts for V
DD
and from
0.8 to 3.3 volts for the FlexiPower supply. PE3291
features very low power consumption and is
available in a 20-lead TSSOP (JEDEC MO-153-
AC) package.
FlexiPower Operation
Each FlexiPower PLL prescaler can be supplied
its own dedicated supply voltage as low as 0.8
volts for substantial power savings. The maximum
frequency of operation scales with the FlexiPower
supply voltage. If voltages less than V
DD
are not
available, the FlexiPower supplies can be
internally generated, but the power savings will
not be as great as when using external
FlexiPower supplies.
Spurious Response
A critical parameter for synthesizer designs is
spurious output. Spurs occur at the integer
multiples of the step size away from center tone.
An important feature of fractional synthesizers is
their ability to reduce these spurious sidebands.
The PE3291 has a built-in method for reducing
these spurs, with no external components or
tuning required. In addition, this circuitry works
over the full commercial temperature range.
Figure 4. PE3291 Block Diagram
f
in
1
32/33
Prescaler
19-bit Fractional-N
Main Divider
Fractional Spur
Compensation
f
r
Ref.
Amp.
9-bit Reference
Divider
Phase
Detector
Charge
Pump
CP1
Clock
Data
LE
21-bit Serial Control
Interface
Multiplexer
f
o
LD
9-bit Reference
Divider
Phase
Detector
Charge
Pump
CP2
f
in
2
16/17
Prescaler
18-bit Fractional-N
Main Divider
Fractional Spur
Compensation
Document No. 70-0009-04
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©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 15
PE3291
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
V
DD
V
I
I
I
I
O
T
stg
Table 3. Operating Ratings
Units
V
V
mA
mA
°C
Parameter/Conditions
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature
range
Min
-0.3
-0.3
-10
-10
-65
Max
4.0
V
DD
+ 0.3
+10
+10
150
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
Min
2.7
-40
Max
3.3
85
Units
V
°C
Table 4. ESD Ratings
Symbol
V
ESD
Note 1:
Parameter/Conditions
ESD voltage human body model
Level
1000
Units
V
Absolute Maximum Ratings are those values listed in
the above table. Exceeding these values may cause
permanent device damage. Functional operation
should be restricted to the limits in the DC and AC
Characteristics table. Exposure to absolute maximum
ratings for extended periods may affect device
reliability.
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics:
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
I
DD
Parameter
3 V supply current when V
DD1
and V
DD2
are internally
regulated down from V
DD
(note 1)
Conditions
(10 MHz Ref. Freq.)
P
2
, P
1
= 01 RF
RF PLL1 low speed
P
2
, P
1
= 1X
C
10
, C
20
= 01
P
2
, P
1
= 01
C
10
, C
20
= 00
P
2
, P
1
= 10
C
10
, C
20
= 00
P
2
, P
1
= 11
C
10
, C
20
= 00
P
2
, P
1
= 00
RF PLL1 high speed
IF PLL2 off
RF PLL1 low speed
IF PLL2 low speed
RF PLL1 high speed
IF PLL2 low speed
RF PLL1 high speed
IF PLL2 high speed
2 PLL’s enabled
1 PLL enabled
Min
Typ
1.4
2.0
2.1
2.7
3.1
1.0
0.7
Max
Units
mA
mA
mA
mA
mA
mA
mA
I
DD
3 V supply current when V
DD1
and V
DD2
are externally
supplied (note 1)
PLL1 FlexiPower Prescaler
supply current (see fig. 5)
I
DD1
P
2
, P
1
= 00
V
DD1
= 1/0 volt
V
DD1
= 1.8 volts
V
DD1
= 2.7 volts
P2, P1 = 00
V
DD2
= 1.0 volt
V
DD2
= 1.8 volts
V
DD2
= 2.7 volts
PLL1 enabled
0.5
1.5
4.0
PLL2 enabled
0.4
1.2
2.0
5
0.7 x V
DD
0.3 x V
DD
-1
-1
+1
+1
mA
mA
mA
mA
V
V
mA
mA
mA
mA
mA
I
DD2
PLL2 FlexiPower Prescaler
supply current (see fig. 5)
I
stby
Total standby current
Digital inputs: Clock, Data, LE
V
IH
High level input voltage
V
IL
Low level input voltage
I
IH
I
IL
High level input current
Low level input current
50
V
DD
= 2.7 to 3.3 volts
V
DD
= 2.7 to 3.3 volts
V
IH
= V
DD
= 3.3 volts
V
IL
= 0, V
DD
= 3.3 volts
Note 1:
The total current consumed by the device is I
DD
when internal regulation is employed and I
DD
+ I
DD1
+ I
DD2
when V
DD1
and V
DD2
are
externally supplied. When V
DD1
and V
DD2
are internally generated, pins 7 and 14 should be left floating.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0009-04
│
UltraCMOS™ RFIC Solutions
PE3291
Product Specification
Table 5. DC Characteristics (continued):
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
Reference Divider input: f
r
I
IHR
I
ILR
V
OLD
V
OHD
I
CP - Source
I
CP - Sink
I
CPL
I
CP – Source
vs.
I
CP
vs. T
A
I
CP
vs. V
CP
Sink vs. Source mismatch
Output current vs. temperature
Output current magnitude variation vs.
voltage
V
CP
= V
DD
/ 2, T
A
= 25° C
V
CP
= V
DD
/ 2
0.5 V < V
CP
< V
DD
– 0.5
volt, T
A
= 25° C
10
10
10
%
%
%
Input current
Input current
Output voltage LOW
Output voltage HIGH
V
IH
= V
DD
= 3.6 volts
V
IL
= 0, V
DD
= 3.6 volts
I
out
= 1 mA
I
out
= -1 mA
V
DD
-0.4
-70
70
-5
5
-25
+25
mA
mA
V
V
mA
mA
nA
Parameter
Conditions
Min
Typ
Max
Units
Digital output: f
o
LD
Charge Pump outputs: CP1, CP2
Drive current
Leakage current
VC
P
= V
DD
/ 2
0.5 V < V
CP
< V
DD
-0.5 volt
Figure 5. Prescaler Current vs. FlexiPower Voltage (V
DD1
and V
DD2
externally supplied)
4 0
.0
3.0
0
P L
L 1
PL 2
L
Typic al Cur r ent
( mA)
2 0
.0
1.0
0
0 0
.0
0.8
1.2
1
.6
2
2
.4
DD
1
2.8
D
D2
3.2
FlexiPow r vo ge (V
e
lta
,V
)
Table 6. AC Characteristics:
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
f
Clk
t
ClockH
t
ClockL
t
DSU
t
DHLD
t
LEW
t
CLE
t
LEC
t
Data Out
Parameter
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Data set-up time to Clock rising edge
Data hold time after Clock rising edge
LE pulse width
Clock falling edge to LE rising edge
LE falling edge to Clock rising edge
Data Out delay after Clock falling edge (f
o
LD pin)
C
L
= 50 pf
Conditions
Min
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Control Interface and Latches (see figure 8)
50
50
50
10
50
50
50
90
ns
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©2005 Peregrine Semiconductor Corp. All rights reserved.
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