HY57V653220B
4 Banks x 512K x 32Bit Synchronous DRAM
Preliminary
DESCRIPTION
The Hyundai HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the memory applica-
tions which require wide data I/O and high bandwidth. HY57V653220B is organized as 4banks of 524,288x32.
HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
•
•
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
Internal four banks operation
•
•
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
•
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
•
•
ORDERING INFORMATION
Part No.
HY57V653220BTC-6
HY57V653220BTC-7
HY57V653220BTC-8
HY57V653220BTC-10
HY57V653220BLTC-6
HY57V653220BLTC-7
HY57V653220BLTC-8
HY57V653220BLTC-10
Clock Frequency
166MHz
143MHz
Power
Organization
Interface
Package
Normal
125MHz
100MHz
166MHz
143MHz
Low power
125MHz
100MHz
4Banks x 512Kbits
x32
LVTTL
400mil 86pin TSOP II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.7/Apr.99
HY57V653220B
PIN CONFIGURATION
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
S S Q
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
S S Q
DQ7
NC
V
DD
DQM0
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
V
D D
NC
DQ16
V
S S Q
DQ17
DQ18
V
DDQ
DQ19
DQ20
V
S S Q
DQ21
DQ22
V
DDQ
DQ23
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
S S Q
DQ14
DQ13
V
D D Q
DQ12
DQ11
V
S S Q
DQ10
DQ9
V
D D Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
D D Q
DQ30
DQ29
V
S S Q
DQ28
DQ27
V
D D Q
DQ26
DQ25
V
S S Q
DQ24
V
SS
8 6 pin TSOP II
400mil x 875mil
0.5mm pin pitch
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A10
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.7/Apr.99
2
HY57V653220B
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD,
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260
⋅
10
Rating
°C
°C
V
V
mA
W
°C ⋅
Sec
Unit
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
(TA=0 to 70°C)
Parameter
Power Supply Voltage
Input high voltage
Input low voltage
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Min
3.0
2.0
V
SSQ
- 0.3
Typ.
3.3
3.0
0
Max
3.6
V
DDQ
+ 0.3
0.8
Unit
V
V
V
Note
1,2
1,3
1,4
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
DD/
V
DDQ
(min) is 3.15V for HY57V653220B(L)TC-6
3.V
IH
(max) is acceptable 5.6V AC pulse width with
≤3ns
of duration with no input clamp diodes
4.V
IL
(min) is acceptable -2.0V AC pulse width with
≤3ns
of duration with no input clamp diodes
AC OPERATING CONDITION
(TA=0 to 70°C, 3.0V
≤V
DD
≤3.6V,
V
SS
=0V - Note1)
Parameter
AC input high / low level voltage
Input timing measurement reference level voltage
Input rise / fall time
Output timing measurement reference level
Output load capacitance for access time measurement
Symbol
V
IH
/ V
IL
Vtrip
tR / tF
Voutref
CL
Value
2.4/0.4
1.4
1
1.4
30
Unit
V
V
ns
V
pF
2
Note
Note :
1.3.15V
≤V
DD
≤3.6V
is applied for HY57V653220B(L)TC-6
2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Rev. 0.7/Apr.99
3
HY57V653220B
CAPACITANCE
(TA=25°C, f=1MHz, VDD=3.3V)
Parameter
Input capacitance
CLK
A0 ~ A10, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
Data input / output capacitance
DQ0 ~ DQ31
Pin
Symbol
C
I1
CI
2
Min
2.5
2.5
Max
4
5
Unit
pF
pF
C
I/O
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
Vtt=1.4V
RT=500
Ω
RT=50
Ω
Output
Output
30pF
Z0 = 50Ω
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I
(DC operating conditions unless otherwise noted)
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
I
LI
I
LO
V
OH
V
OL
Symbol
Min.
-1
-1.5
2.4
-
Max
1
1.5
-
0.4
Unit
uA
uA
V
V
Note
1
2
I
OH
= -2mA
I
OL
= +2mA
Note :
1.V
IN
= 0 to 3.6V, All other pins are not under test = 0V
2.D
OUT
is disabled, V
OUT
=0 to 3.6V
Rev. 0.7/Apr.99
4
HY57V653220B
DC CHARACTERISTICS II
(DC operating conditions unless otherwise noted)
Speed
Parameter
Symbol
Test Condition
-6
Burst Length=1, One bank active
tRAS
≥
tRAS(min), tRP
≥
tRP(min),
IOL=0mA
CKE
≤
VIL(max), tCK = 15ns
CKE
≤
VIL(max), tCK =
∞
CKE
≥
VIH(min), CS
≥
VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins
≥
VDD-0.2V or
≤
0.2V
CKE
≥
VIH(min), tCK =
∞
Input signals are stable.
CKE
≤
VIL(max), tCK = 15ns
CKE
≤
VIL(max), tCK =
∞
CKE
≥
VIH(min), CS
≥
VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins
≥
VDD-0.2V or
≤
0.2V
CKE
≥
VIH(min), tCK =
∞
Input signals are stable
tCK
≥
tCK(min),
tRAS
≥
tRAS(min), IOL=0mA
All banks active
tRRC
≥
tRRC(min), All banks active
CKE
≤
0.2V
CL=3
CL=2
240
160
220
210
160
210
2
500
-7
-8
-10
Unit
Note
Operating Current
IDD1
180
170
150
150
mA
1
Precharge Standby Current
in power down mode
IDD2P
IDD2PS
2
mA
2
IDD2N
Precharge Standby Current
in non power down mode
IDD2NS
IDD3P
IDD3PS
15
mA
10
3
mA
3
Active Standby Current
in power down mode
IDD3N
Active Standby Current
in non power down mode
IDD3NS
40
mA
25
180
160
190
160
mA
160
190
mA
mA
uA
2
3
4
1
Burst Mode Operating Current
IDD4
Auto Refresh Current
IDD5
Self Refresh Current
IDD6
Note :
1.I
DD1
and I
DD4
depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V653220BTC-6/7/8/10
4.HY57V653220BLTC--6/7/8/10
Rev. 0.7/Apr.99
5
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