DATASHEET
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER
Description
The ICS348 field programmable clock synthesizer
generates up to 9 high-quality, high-frequency clock outputs
including multiple reference clocks from a low frequency
crystal or clock input. The ICS348 has 4 independent
on-chip PLLs and is designed to replace crystals and
crystal oscillators in most electronic systems.
Using IDT’s VersaClock software to configure PLLs and
outputs, the ICS348 contains a One-Time Programmable
(OTP) ROM to allow field programmability. Programming
features include eight selectable configuration registers, up
to two sets of four low-skew outputs.
Using Phase-Locked Loop (PLL) techniques, the device
runs from a standard fundamental mode, inexpensive
crystal, or clock. It can replace multiple crystals and
oscillators, saving board space and cost.
The ICS348 is also available in factory programmed custom
versions for high-volume applications.
TM
ICS348
Features
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Packaged as 20-pin SSOP (QSOP)
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3V
Input crystal frequency of 5 to 27 MHz
Input clock frequency of 2 to 50 MHz
Up to nine reference outputs
Up to two sets of four low-skew outputs
Operating voltages of 3.3 V
Advanced, low power CMOS process
For one output clock, use the ICS341 (8-pin). For two
output clocks, use the ICS342 (8-pin). For three output
clocks, use the ICS343 (8-pin). For more than three
outputs, use the ICS345 or ICS348.
•
Available in Pb (lead) free packaging
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
V DD
3
S 2:S 0
3
O TP
ROM
w ith
P LL
V alues
P LL1
CLK1
CLK2
P LL2
P LL3
C rystal or
clock input
X 1/IC LK
C rystal
O scillator
X2
GND
2
P LL4
Divide
Logic
and
Output
Enable
Control
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
E xternal capacitors are
required w ith a crystal input.
P D TS
IDT™ / ICS™
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER 1
ICS348
REV K 092109
ICS348
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Pin Assignment
X1/ICLK
S0
S1
CLK9
VDD
GND
CLK1
CLK2
CLK3
CLK4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
X2
VDD
PDTS
S2
VDD
GND
CLK5
CLK6
CLK7
CLK8
20-pin (150 mil) SSOP (QSOP)
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
X1
S0
S1
CLK9
VDD
GND
CLK1
CLK2
CLK3
CLK4
CLK8
CLK7
CLK6
CLK5
GND
VDD
S2
PDTS
VDD
X2
Pin
Type
XI
Input
Input
Output
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Input
Input
Power
XO
Pin Description
Crystal Input. Connect this pin to a crystal or external input clock.
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Output clock 9. Weak internal pull-down when tri-state.
Connect to +3.3 V.
Connect to ground.
Output clock 1. Weak internal pull-down when tri-state.
Output clock 2. Weak internal pull-down when tri-state.
Output clock 3. Weak internal pull-down when tri-state.
Output clock 4. Weak internal pull-down when tri-state.
Output clock 8. Weak internal pull-down when tri-state.
Output clock 7. Weak internal pull-down when tri-state.
Output clock 6. Weak internal pull-down when tri-state.
Output clock 5. Weak internal pull-down when tri-state.
Connect to ground.
Connect to +3.3 V.
Select pin 2. Internal pull-up resistor.
Power down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
Connect to +3.3 V.
Crystal Output. Connect this pin to a fundamental crystal. Float for clock input.
IDT™ / ICS™
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER 2
ICS348
REV K 092109
ICS348
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω
.
they should be separated and away from other traces.
3) To minimize EMI, the 33Ω series termination resistor, if
needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS348
must be isolated from system power supply noise to perform
optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
ICS348 Configuration Capabilities
The architecture of the ICS348 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS348 also provides separate output divide values,
from 2 through 20, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented as:
OutputFreq
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance
of the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-6
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
=
REFFreq
-------------------------------------
-
OutputDivide
⋅
M
----
-
N
IDT VersaClock Software
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
IDT™ / ICS™
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER 3
ICS348
REV K 092109
ICS348
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS348. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Supply Voltage, VDD
Inputs
Clock Outputs
Storage Temperature
Soldering Temperature
Junction Temperature
Condition
Referenced to GND
Referenced to GND
Referenced to GND
Max 10 seconds
Min.
-0.5
-0.5
-65
Typ.
Max.
7
VDD+0.5
VDD+0.5
150
260
125
Units
V
V
V
°
C
°
C
°
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS348RP)
Ambient Operating Temperature (ICS348RIP)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
Min.
0
-40
+3.15
Typ.
Max.
+70
+85
Units
°
C
°
C
V
ms
+3.3
+3.45
4
IDT™ / ICS™
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER 4
ICS348
REV K 092109
ICS348
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER
EPROM CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%,
Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Symbol
VDD
Conditions
Configuration Dependent
- See VersaClock
TM
Estimates
Min.
3.15
Typ.
Max.
3.45
Units
V
mA
Operating Supply Current
Input High Voltage
IDD
Nine 33.3333 MHz outs,
PDTS = 1, no load, Note
1
PDTS = 0, no load
S2:S0
S2:S0
VDD-0.5
2
23
mA
20
0.4
0.4
Input High Voltage
Input Low Voltage
Input High Voltage, PDTS
Input Low Voltage, PDTS
Input High Voltage
Input Low Voltage
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
Internal pull-up resistor
Internal pull-down
resistor
Input Capacitance
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
Z
O
R
PUS
R
PD
C
IN
µA
V
V
V
V
V
VDD/2-1
V
V
V
0.4
V
mA
Ω
kΩ
kΩ
pF
ICLK
ICLK
I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= 12mA
VDD/2+1
VDD-0.4
2.4
±70
20
S2:S0, PDTS
CLK outputs
Inputs
250
525
4
Note 1: Example with 25 MHz crystal input with nine outputs of 33.3 MHz, no load, and VDD = 3.3 V.
IDT™ / ICS™
QUAD PLL FIELD PROGRAMMABLE VERSACLOCK SYNTHESIZER 5
ICS348
REV K 092109
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