M87C257
ADDRESS LATCHED
256K (32K x 8) UV EPROM and OTP EPROM
INTEGRATED ADDRESS LATCH
FAST ACCESS TIME: 45ns
LOW POWER “CMOS” CONSUMPTION:
– Active Current 30mA
– Standby Current 100µA
PROGRAMMING VOLTAGE: 12.75V
ELECTRONIC SIGNATURE for AUTOMATED
PROGRAMMING
PROGRAMMING TIMES of AROUND 3sec.
(PRESTO II ALGORITHM)
28
1
FDIP28W (F)
PLCC32 (C)
Figure 1. Logic Diagram
DESCRIPTION
The M87C257 is a high speed 262,144 bit UV
erasable and electrically programmable EPROM.
The M87C257 incorporates latches for all address
inputs to minimize chip count, reduce cost, and
simplify the design of multiplexed bus systems.
The Window Ceramic Frit-Seal Dual-in-Line pack-
age has a transparent lid which allows the user to
expose the chip to ultraviolet light to erase the bit
pattern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M87C257 is offered in Plastic Leaded Chip Carrier,
package.
VCC
15
A0-A14
8
Q0-Q7
E
G
M87C257
Table 1. Signal Names
A0 - A14
Q0 - Q7
E
G
ASV
PP
V
CC
V
SS
Address Inputs
Data Outputs
Chip Enable
Output Enable
Address Strobe / Program Supply
Supply Voltage
Ground
ASVPP
VSS
AI00928B
June 1996
1/13
M87C257
Figure 2A. DIP Pin Connections
Figure 2B. LCC Pin Connections
Q1
Q2
AI00929
VSS
DU
Q3
Q4
Q5
AI00930
ASVPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS
28
1
27
2
26
3
25
4
24
5
23
6
22
7
M87C257
21
8
20
9
19
10
18
11
17
12
13
16
14
15
VCC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5
Q4
Q3
A7
A12
ASVPP
DU
VCC
A14
A13
1 32
A6
A5
A4
A3
A2
A1
A0
NC
Q0
A8
A9
A11
NC
G
A10
E
Q7
Q6
9
M87C257
25
17
Warning:
NC = Not Connected, DU = Dont’t Use.
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltages (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Unit
°C
°C
°C
V
V
V
V
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
DEVICE OPERATION
The modes of operation of the M87C257 are listed
in the Operating Modes. A single power supply is
required in the read mode. All inputs are TTL levels
except for V
PP
and 12V on A9 for Electronic Signa-
ture.
Read Mode
The M87C257 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
2/13
M87C257
Table 3. Operating Modes
Mode
Read (Latched Address)
Read (Applied Address)
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note:
X = V
IH
or V
IL
, V
ID
= 12V
±
0.5V
E
V
IL
V
IL
V
IL
V
IL
Pulse
V
IH
V
IH
V
IH
V
IL
G
V
IL
V
IL
V
IH
V
IH
V
IL
V
IH
X
V
IL
A9
X
X
X
X
X
X
X
V
ID
ASV
PP
V
IL
V
IH
X
V
PP
V
PP
V
PP
X
V
IL
Q0 - Q7
Data Out
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q7
0
1
Q6
0
0
Q5
1
0
Q4
0
0
Q3
0
0
Q2
0
0
Q1
0
0
Q0
0
0
Hex Data
20h
80h
be used to gate data to the output pins, inde-
pendent of device selection. Assuming that the
addresses are stable (AS = V
IH
) or latched (AS =
V
IL
), the address access time (t
AVQV
) is equal to the
delay from E to output (t
ELQV
). Data is available at
the output after delay of t
GLQV
from the falling edge
of G, assuming that E has been low and the ad-
dresses have been stable for at least t
AVQV
-t
GLQV
.
The M87C257 reduces the hardware interface in
multiplexed address-data bus systems. The proc-
essor multiplexed bus (AD0-AD7) may be tied to
the M87C257’s address and data pins. No sepa-
rate address latch is needed because the
M87C257 latches all address inputs when AS is
low.
Standby Mode
The M87C257 has a standby mode which reduces
the active current from 30mA to 100µA (Address
Stable). The M87C257 is placed in the standby
mode by applying a CMOS high signal to the E
input. When in the standby mode, the outputs are
in a high impedance state, independent of the G
input.
Two Line Output Control
Because EPROMs are usually used in larger mem-
ory arrays, this product features a 2 line control
function which accommodates the use of multiple
memory connection. The two line control function
allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control lines,
E should be decoded and used as the primary
device selecting function, while G should be made
a common connection to all devices in the array
and connected to the READ line from the system
control bus. This ensures that all deselected mem-
ory devices are in their low power standby mode
and that the output pins are only active when data
is desired from a particular memory device.
3/13
M87C257
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
Standard
≤
20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
3.3kΩ
1N914
Standard
2.4V
2.0V
0.8V
AI01822
OUT
CL = 30pF or 100pF
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823
Table 6. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note:
1. Sampled only, not 100% tested.
System Considerations
The power switching characteristics of Advance
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
this transient current peaks is dependent on the
capacitive and inductive loading of the device at the
output. The associated transient voltage peaks can
be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capacitor
of low inherent inductance and should be placed
as close to the device as possible. In addition, a
4.7µF bulk electrolytic capacitor should be used
between V
CC
and V
SS
for every eight devices. The
bulk capacitor should be located near the power
supply connection point. The purpose of the bulk
capacitor is to overcome the voltage drop caused
by the inductive effects of PCB traces.
4/13
M87C257
Table 7. Read Mode DC Characteristics
(1)
(T
A
= 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
I
CC
I
CC1
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current
(Standby) TTL
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
E = V
IH
, ASV
PP
= V
IH
, Address Switching
E = V
IH
, ASV
PP
= V
IL
, Address Stable
E
≥
V
CC
– 0.2V, ASV
PP
≥
V
CC
– 0.2V,
Address Switching
E
≥
V
CC
– 0.2V, ASV
PP
= V
SS
,
Address Stable
V
PP
= V
CC
–0.3
2
I
OL
= 2.1mA
I
OH
= –1mA
V
CC
– 0.8V
Min
Max
±10
±10
30
10
1
6
100
100
0.8
V
CC
+ 1
0.4
Unit
µA
µA
mA
mA
mA
mA
µA
µA
V
V
V
V
I
CC2
Supply Current (Standby)
CMOS
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Notes:
1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(T
A
= 0 to 70°C, –40 to 85°C, –40 to 105°C or –40 to 125°C; V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Symbol
Alt
Parameter
Address Valid to
Output Valid
Address Valid to
Address Strobe Low
Address Strobe High
to Address Strobe Low
Address Strobe Low to
Address Transition
Address Strobe Low to
Output Enable Low
Chip Enable Low to
Output Valid
Output Enable Low to
Output Valid
Chip Enable High to
Output Hi-Z
Output Enable High to
Output Hi-Z
Address Transition to
Output Transition
G = V
IL
E = V
IL
G = V
IL
E = V
IL
E = V
IL
,
G = V
IL
0
0
0
Test
Condition
E = V
IL
, G = V
IL
7
35
20
20
45
25
25
25
0
0
0
M87C257
-45
(3)
-60
-70
-80
Unit
Min Max Min Max Min Max Min Max
t
AVQV
t
AVASL
t
ASHASL
t
ASLAX
t
ASLGL
t
ELQV
t
GLQV
t
EHQZ
(2)
t
ACC
t
AL
t
LL
t
LA
t
LOE
t
CE
t
OE
t
DF
t
DF
t
OH
45
7
60
7
35
20
20
60
30
30
30
0
0
0
35
20
20
70
7
35
20
20
70
35
30
30
0
0
0
80
ns
ns
ns
ns
ns
80
40
40
40
ns
ns
ns
ns
ns
t
GHQZ (2)
t
AXQX
Notes:
1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
3. In case of 45ns speed see High Speed AC measurement conditions.
5/13
FPGA/CPLD
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