PRELIMINARY
NJW1146
Audio Processor with BBE
s
GENERAL DESCRIPTION
NJW1146
is an audio processor with BBE, which also includes Master
volume, Balance, Tone Control, eala(original surround), Mute, and Output
2
filter amplifier. All of internal status and variables are controlled by I C
BUS.
s
FEATURES
q
Operating Voltage
2
q
I C Bus interface
q
BBE
q
eala & simulated stereo
q
Master Volume
q
Balance
qTone
Control
q
Bi-CMOS
q
Package Outline
8 to 10 V
0 to +15dB(0.5dB/step)
0 to -80dB, MUTE(0.33dB/step)
0 to -30dB, MUTE(1dB/step)
-15 to +15dB(0.5dB/step)
SDMP30
s
PACKAGE OUTLINE
NJW1146M
s
BLOCK DIAGRAM
TONE-Ha
TONE-La
BBE-Ha
BBE-La
eala Fil
OUTa
LFINa
LFOUTa
AGC
SCL
SDA
Ina
AGC
Vol1
BBE
Tone
Vol2
Buffer
CBH
CBL
CVA
CVB
CTH
CTL
CSR
Inb
Vol1
BBE
Tone
Vol2
Buffer
I
2
C Bus Interface
eala
Bias
V+
GND
TONE-Hb
TONE-Lb
BBE-Hb
BBE-Lb
LFOUTb
OUTb
LFINb
Vref
–1–
NJW1146
s
PIN FUNCTION
PRELIMINARY
30
16
1
15
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SYMBOL
INa
ealaFil
BBE1a
BBE2a
TONE-Ha
TONE-La
OUTa
LFINa
LFOUTa
AGC
CVA
CVB
SDA
SCL
GND
FUNCTION
A ch Input
eala Filter Capacitor
Ach BBE High-Pass Filter Capacitor
Ach BBE Low-Pass Filter Capacitor
Ach TONE Treble Filter Capacitor
Ach TONE Bass Filter Capacitor
Ach Output
Buffer Input for Ach Low Pass Filter
Buffer Output for Ach Low Pass Filter
AGC Smoothing Filter Capacitor
Ach Volume switching noise rejection Capacitor
Bch Volume switching noise rejection Capacitor
I
2
C Data Input
I
2
C Clock Input
Ground
No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SYMBOL
V+
VREF
CTL
CTH
CBL
CBH
LFOUTb
LFINb
OUTb
TONE-Lb
TONE-Hb
BBE2b
BBE1b
CSR
INb
FUNCTION
Power Supply
Reference Voltage stabilizing Capacitor
Tone Control Bass switching noise rejection Capacitor
Tone Control Treble switching noise rejection Capacitor
BBE Low switching noise rejection Capacitor
BBE High switching noise rejection Capacitor
Buffer Output for Bch Low Pass Filter
Buffer Input for Bch Low Pass Filter
Bch Output
Bch TONE Bass Filter Capacitor
Bch TONE Treble Filter Capacitor
Bch BBE Low-Pass Filter Capacitor
Bch BBE High-Pass Filter Capacitor
eala switching noise rejection Capacitor
B ch Input
–2–
PRELIMINARY
NJW1146
s
ABSOLUTE MAXIMUM RATING (Ta=25°C)
°
PARAMETER
SYMBOL
Supply Voltage
Power Dissipation
Operating Temperature Range
Storage Temperature Range
s
ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Voltage
Supply Current
Reference Voltage
Maximum Input Voltage
Maximum Output Voltage
Channel Balance
Balance Boost A
Balance Cut A
Balance Boost B
Balance Cut B
Total Harmonic Distortion
Maximum Voltage Gain
Minimum Voltage Gain
Channel Separation
Output Noise 1
Output Noise 2
V
+
RATING
12
700
-20 to +75
-40 to +125
+
UNIT
V
mW
°C
°C
P
D
Topr
Tstg
MODE ; VOL=0dB, BAL=0dB, AGC=OFF, BBE=OFF, Tone=0dB, eala=By-Pass)
(Ta=25°C, V =9V, R
L
=47kΩ, Vin=100mVrms/1kHz
°
TEST CONDITION
No Signal
No Signal
VOL=-20dB,THD=10%
OUTPUT
VOL=0dB,THD=1%
VOL=0dB
CHS=”0”,BAL=Mute
CHS=”1”,BAL=Mute
Vin = 1Vrms
CHS=”1”,BAL=Mute
CHS=”0”,BAL=Mute
Vin = 1Vrms
Vo=0.5Vrms
BW=400Hz to 30kHz
VOL= 0dB
VOL= Mute
Vin = 1Vrms
VOL = 0dB
BW=400Hz to 30kHz
VOL = Mute
BW = 400Hz to 30kHz
+
SYMBOL
V
+
MIN.
8.0
-
4.0
2.8
-
-1.5
-2.0
-
-2.0
-
-
-2.0
-
-
-
-
-
-
TYP.
9.0
25
4.5
3.0
2.5
0.0
0.0
-
0.0
-
-
0.0
-
-
-90
(31.6)
-106
(5.0)
MAX.
10.0
35
5.0
-
-
1.5
2.0
-70
2.0
-70
0.5
2.0
-70
-70
-85
(56.2)
-96
(15.8)
UNIT
V
mA
V
Vrms
Vrms
dB
dB
dB
dB
dB
%
dB
dB
dB
dBV
(µVrms)
dBV
(µVrms)
I
CC
V
REF
V
IM
V
OM
G
CB
G
BBA
G
BCA
G
BBB
G
BCB
THD
G
VMAX
G
VMIN
CS
V
NO1
V
NO2
BW : Band Width
x
TONE CONTROL CHARACTERISTICS
PARAMETER
Treble Boost Gain
Treble Boost Flat
Treble Boost Cut
Bass Boost Gain
Bass Boost Flat
Bass Boost Cut
SYMBOL
G
HFBST
G
HFFLT
G
HFCUT
G
LFBST
G
LFFLT
G
LFCUT
MODE ; VOL=0dB, BAL=0dB, AGC=OFF, BBE=OFF, eala=By-Pass)
(Ta=25°C, V =9V, R
L
=47kΩ, Vin=100mVrms/1kHz
TEST CONDITION
TREB=+15dB, f=10kHz
TREB=0dB,f=10kHz
TRBE=-15dB, f=10kHz
BASS=+15dB, f=100Hz
BASS=0dB, f=100Hz
BASS=-15dB, f=100Hz
MIN.
12.5
-2.0
-17.5
12.5
-2.0
-17.5
TYP.
15.0
0.0
-15.0
15.0
0.0
-15.0
MAX.
17.5
2.0
-12.5
17.5
2.0
-12.5
UNIT
dB
dB
dB
dB
dB
dB
–3–
NJW1146
x
AGC CHARACTERISTICS
PARAMETER
AGC Boost
AGC Flat 1
AGC Flat 2
AGC Flat 3
AGC Flat 4
AGC Cut
x
BBE CHARACTERISTICS
PARAMETER
Low Boost Gain
High Boost Gain
x
eala CHARACTERISTICS
PARAMETER
Simulated Stereo A
Simulated Stereo B
Surround 3D1
Surround 3D2
Surround 3D3
Surround 3D4
2
+
PRELIMINARY
(Ta=25°C, V =9V, R
L
=47kΩ
SYMBOL
G
AGCBST
G
AGCFLT1
G
AGCFLT2
G
AGCFLT3
G
AGCFLT4
G
AGCCUT
+
MODE ; VOL=0dB, BAL=0dB, AGC=ON, BBE=OFF, Tone=0dB, eala=By-Pass)
TEST CONDITION
Vin=50mVrms, f=1kHz
Vin=300mVrms, f=1kHz
Vin=400mVrms, f=1kHz
Vin=500mVrms, f=1kHz
Vin=600mVrms, f=1kHz
Vin=2Vrms, f=1kHz
MIN.
1.5
-2.5
-2.5
-2.5
-2.5
-14
TYP.
3.5
0.0
0.0
0.0
0.0
-10
MAX.
5.5
2.5
2.5
2.5
2.5
-6.0
UNIT
dB
dB
dB
dB
dB
dB
MODE ; VOL=0dB, BAL=0dB, AGC=OFF, Tone=0dB, eala=By-Pass)
(Ta=25°C, V =9V, R
L
=47kΩ, Vin=100mVrms/1kHz
SYMBOL
G
BBELOW
G
BBEHIGH
+
TEST CONDITION
BBE-LOW =+15dB, f=50Hz
BBE-HIGH =+15dB, f=10kHz
MIN.
12.5
12.5
TYP.
15
15
MAX.
17.5
17.5
UNIT
dB
dB
MODE ; VOL=0dB, BAL=0dB, AGC=OFF, BBE=0dB, Tone=0dB)
(Ta=25°C, V =9V, R
L
=47kΩ, Vin=100mVrms/1kHz
SYMBOL
G
SIMA
G
SIMB
G
3D1
G
3D2
G
3D3
G
3D4
TEST CONDITION
LIN+RIN→OUTa, f=1KHz, SIM
LIN+RIN→OUTb, f=1KHz, SIM
LIN
→
OUTa, f=100Hz, SR2
LIN
→
OUTa, f=10KHz, SR2
LIN
→
OUTb, f=100Hz, SR2
LIN
→
OUTa, f=100Hz, SR1
MIN.
1.0
1.0
5.5
-2.0
0.5
3.5
TYP.
3.0
3.0
7.5
0.0
2.5
5.5
MAX.
5.0
5.0
9.5
2.0
4.5
7.5
UNIT
dB
dB
dB
dB
dB
dB
s
I C BUS CHARACTERISTICS (SDA, SCL)
I C BUS Load Conditions: Pull up resistance 4kΩ(Connected to +5V), Load capacitance 200pF (Connected to GND)
2
PARAMETER
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Low Level Output Voltage (3mA at SDA pin)
Maximum Output Current
Maximum Clock Frequency
Data Change Minimum Waiting Time
Data Transfer Start Minimum Waiting Time
Low Level Clock Pulse Width
High Level Clock Pulse Width
Minimum Start Preparation Waiting Time
Minimum Data Hold Time
Minimum Data Preparation Time
Rise Time
Fall Time
Minimum Stop Preparation Waiting Time
SYMBOL
V
IH
V
IL
I
IH
I
IL
V
OL
I
OL
f
SCL
t
BUF
t
HD:STA
t
LOW
T
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
MIN.
3.0
0
-
-
0
-3.0
0
4.7
4.0
4.7
4.0
4.7
5.0
250
-
-
4.7
TYP.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX.
5.0
1.5
10
10
0.4
-
100
-
-
-
-
-
-
-
1.0
300
-
UNIT
V
V
µA
µA
V
mA
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
–4–
PRELIMINARY
NJW1146
SDA
t
BU
t
R
t
F
t
HD:ST
SCL
t
HD:ST
P
S
t
LOW
t
HD:DA
t
HIGH
t
SU:DA
Sr
t
SU:ST
t
SU:ST
P
–5–
嵌入式系统
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