PRELIMINARY
This Preliminary data sheet provides detailed functional
capabilities for product currently in prototype production.
These specifications are being provided to allow for
electrical design, layout and operation.
BU-62743/62843/62864
PCI ENHANCED MINIATURE ADVANCED COMMUNICATION ENGINE
(PCI ENHANCED MINI-ACE)
FEATURES
•
•
•
•
32-Bit / 33Mhz, 3.3Volt, PCI Target Interface
Fully Integrated 1553A/B Notice 2, McAir, STANAG 3838 Interface
Terminal
Compatible with Enhanced Mini-ACE, Mini-ACE (Plus) and ACE
Generations
Choice of:
-
RT only with 4K RAM
-
BC/RT/MT with 4K RAM
-
BC/RT/MT with 64K RAM, with RAM Parity
3.3V Logic
5V Transceiver. Available with 1760 or McAir Compatible Options
1.0-inch square, 72-Pin Flatpack / Formed Gull Lead Ceramic Package.
0.815-inch square, 128-Ball BGA also available.
Choice of 10, 12, 16, or 20 MHz 1553 Clock
Highly Autonomous BC With Built-in Message Sequence Control:
-
Frame Scheduling
-
Branching
-
Asynchronous Message Insertion
-
General Purpose Queue
-
User-defined Interrupts
•
Advanced RT Functions
-
Global Circular Buffering
-
Interrupt Status Queue
-
50% Circular Buffer Rollover Interrupts
1
62743_pre2.DOC
8-15-01
•
•
•
•
•
Data Device Corporation
www.ddc-web.com
DESCRIPTION
The PCI Enhanced Mini-ACE family of MIL-STD-1553 terminals provides a
complete interface between a 32-Bit / 33Mhz PCI Bus and a MIL-STD-1553 bus.
These terminals integrate dual transceiver, protocol logic, and 4K words or 64K
words of RAM.
With a 1.0-inch square package, the PCI Enhanced Mini-ACE is nearly 100%
footprint and software compatible with the Enhanced Mini-ACE, previous
generation Mini-Ace (Plus) terminals, and is software compatible with the older
ACE series.
The PCI Enhanced Mini-ACE is powered by 3.3V (3.3V logic). Multiprotocol
support of MIL-STD-1553A/B and STANAG 3838, including versions
incorporating McAir compatible transmitters, is provided. There is a choice of 10,
12, 16, or 20 MHz 1553 clocks. The BC/RT/MT versions with 64K words of RAM
include built-in RAM parity checking.
BC features include a built-in message sequence control engine, with a set of 20
instructions. This provides an autonomous means of implementing multi-frame
message scheduling, message retry schemes, data double buffering,
asynchronous message insertion, and reporting to the host CPU.
The PCI Enhanced Mini-ACE RT offers the same choices of subaddress
buffering as the ACE, Mini-ACE (Plus) and Enhanced Mini-ACE, along with a
global circular buffering option, 50% rollover interrupt for circular buffers, an
interrupt status queue, and an “Auto-boot” option to support MIL-STD-1760.
Data Device Corporation
www.ddc-web.com
2
62743_pre2.DOC
8-15-01
T/R_A
4K 16
OR
64K 17
SHARED
RAM
TRANSCEIVER
A
CH. A
32 32
WRITE
IO
AD31-AD0
PAR
T/R_A
TRANSMITTER
INHIBITS
T_INH_A/B
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMOR
MANAGEMENT
C/BE3-C/BE0
RAME, IRD,
IDSEL
ADDRESS BUS
33 MH,
32-BIT
PCI
CH. B
TRANSCEIVER
B
SLAVE
INTERACE
(PCI) CLK
T/R_B
TRD,STOP,
DEVSEL, PERR, SERR
PCI
Address/Data,
Parity,
and
Bus Command /
Byte Enable
T/R_B
PCI CONTROL
PCI CLK
RT ADDRESS
AND
ADDRESS LATCH
RTAD4-RTAD0, RTADP
RT-AD-LAT
INCMD/MCRST
INT A
PCI INTERRUPT
MISCELLANEOUS
CLK_IN,
MSTCLR,SSLAG/ET_TRG
Figure 1. PCI Enhanced Mini-ACE Block Diagram
Data Device Corporation
www.ddc-web.com
3
62743_pre2.DOC
8-15-01
Table 1. PCI Enhanced Mini-ACE Specifications
PARAMETER
MIN
TYP
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
!
Logic +3.3V
!
RAM +5V
!
Transceiver +5 V (Note 11)
Logic
!
Voltage Input Range for PCI Signals
!
Voltage Input Range for Non PCI Signals
RECEIVER
Differential Input Resistance (Notes 1-6)
Differential Input Capacitance (Notes 1-6)
Threshold Voltage, Transformer Coupled
Common Mode Voltage (Note 7)
TRANSMITTER
Differential Output Voltage
!
Direct Coupled Across 35 ohms, Measured on Bus
!
Transformer Coupled Across 70 ohms
(BU-62XXXXX-XX0,
BU-62XXXXX-XX2) (Note 13)
Output Noise, Differential (Direct Coupled)
Output Offset Voltage, Transformer Coupled Across 70
ohms
Rise/Fall Time
(BU-62XXXX3,
BU-62XXXX4)
LOGIC
V
IH
All signals except CLK_IN
CLK_IN
V
IL
All signals except CLK_IN
CLK_IN
Schmidt Hysteresis
All signals except CLK_IN
CLK_IN
I
IH
, I
IL
All signals except CLK_IN
I
IH
(V
CC
=3.6V, V
IN
=V
CC
)
I
IH
(V
CC
=3.6V, V
IN
=2.7V)
I
IL
(V
CC
=3.6V, V
IN
=0.4V)
CLK_IN
I
IH
I
IL
V
OH
(V
CC
=3.0V, V
IH
=2.7V, V
IL
=0.2V, I
OH
=max)
V
OL
(V
CC
=3.0V, V
IH
=2.7V, V
IL
=0.2V, I
OL
=max)
I
OL
Data Device Corporation
www.ddc-web.com
4
MAX
UNITS
-0.3
-0.3
-0.3
-0.3
-0.3
2.5
0.200
TBD
6.0
7.0
TBD
TBD
V
V
V
V
V
Kohm
Pf
VP-P
VPEAK
5
0.860
10
6
18
20
-250
7
20
22
150
9
27
27
10
250
V
P-P
V
P-P
V
P-P
mV
P-P
mV
PEAK
100
200
150
250
300
300
ns
ns
2.1
0.8•V
CC
0.7
0.2•V
CC
0.4
1.0
V
V
V
V
V
V
-10
-350
-350
-10
-10
2.4
3.4
10
-33
-33
10
10
0.4
µA
µA
µA
µA
µA
V
V
mA
62743_pre2.DOC
8-15-01
Table 1. PCI Enhanced Mini-ACE Specifications
PARAMETER
I
OH
C
I
(Input Capacitance)
C
IO
(Bi-directional signal Input Capacitance)
PCI LOGIC
V
IH
V
IL
I
IH
(V
CC
=3.6V, V
IN
=V
CC
)
I
IH
(V
CC
=3.6V, V
IN
=2.7V)
I
IL
(V
CC
=3.6V, V
IN
=0.4V)
V
OH
(V
CC
=3.0V, V
IH
=2.7V, V
IL
=0.2V, I
OH
=max)
V
OL
(V
CC
=3.0V, V
IH
=2.7V, V
IL
=0.2V, I
OL
=max)
I
OL
I
OH
C
I
(Input Capacitance)
C
IO
(Bi-directional signal Input Capacitance)
POWER SUPPLY REQUIREMENTS
Voltages/Tolerance
+5V (RAM for 62864)
+3.3V (Logic) V
CC
+5V (Ch. A, Ch. B)
Current Drain (Total Hybrid)
BU-62864XX-XX0
+5 V (RAM, CH A, CH B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
BU-62864XX-XX2
+5 V (RAM, CH A, CH B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
BU-62743XX-XX0, BU-62843XX-XX0
+5 V (CH A, CH B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
BU-62743XX-XX0, BU-62843XX-XX2
+5 V (CH A, CH B)
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
Data Device Corporation
www.ddc-web.com
5
0.5•V
CC
-0.5
T.B.D.
T.B.D.
T.B.D.
0.9•V
CC
T.B.D.
T.B.D.
T.B.D.
T.B.D.
MIN
TYP
50
50
MAX
-3.4
UNITS
mA
Pf
Pf
V
V
µA
µA
µA
V
V
mA
mA
Pf
Pf
V
CC
+0.5
0.3•V
CC
T.B.D.
T.B.D.
T.B.D.
0.1•V
CC
4.5
3.0
4.75
5.0
3.3
5.0
5.5
3.6
5.5
V
V
V
120
225
330
540
40
mA
mA
mA
mA
mA
120
236
352
585
40
mA
mA
mA
mA
mA
100
205
310
520
40
mA
mA
mA
mA
mA
100
216
332
mA
mA
mA
62743_pre2.DOC
8-15-01
FPGA/CPLD
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