Oscillator THT, programmable
Features:
- Standard DIL 8 package
- Low cost high performance
- 3.0 ~ 5.5 volt available
- Tolerance and stability up to ± 25ppm
- Ultra low jitter < 11ps
- Tristate or power down available
Specifications
Frequency range
Frequency stability
Operating temperature
Storage temperature
Programmable voltage
1 ~ 133 MHz
Programmable voltage
1 ~ 100 MHz
Aging (ppm / Year), Ta = 25C, Vdd = 5 / 3.3 V
Programmable output level
APQO 08
1MHz ~ 133MHz
±25ppm ~ ±100ppm
0°C ~ +70°C - -40°C ~ +85°C
-55°C ~ +125°C
4.5V ~ 5.5V
3.0V ~ 3.6V
±5ppm
CMOS / TTL
Remarks
Please specify
Please specify
Please specify
APQO 08
Operating conditions
Description
Vdd
C
TTL
Supply voltage
Max capacitive load on outputs for TTL levels
4.5 V ~ 5.5 V Vdd
£
40 MHz
4.5 V ~ 5.5 V Vdd > 40 ~ 133 MHz
Max capacitive load on outputs for CMOS levels
4.5 V ~ 5.5 V Vdd
£
66 MHz
4.5 V ~ 5.5 V Vdd > 66 ~ 133 MHz
3.0 V ~ 3.6 V Vdd
£
40 MHz
3.0 V ~ 3.6 V Vdd > 40 ~ 100 MHz
Min
3.0
Max
5.5
50
25
50
25
30
15
Unit
V
pF
pF
pF
pF
pF
pF
C
CMOS
Drawing
APQO 08
Dimensions in mm
Order key
O
Part
O=Oscillator
- 50.000000M - APQO 08
Frequency
M=MHz
Type/Package
APQO=programmable QO
08=DIL 8
- 50
Tolerance
±ppm
- 5.0
Voltage
5.0=5.0Volt
3.3=3.3Volt
-A
Temperature
A=
0°C ~ +70°C
/
T
Option
T = Tristate
P = Power down
/
Packaging
blank = Tube
B= -10°C ~ +60°C
C= -10°C ~ +70°C
D= -20°C ~ +70°C
E= -40°C ~ +85°C
auris-GmbH
office@auris-gmbh.de www.auris-gmbh.de
All specifications are subject to change without notice.
3.5
Oscillator THT, programmable
APQO 08
Electrical characteristics
Discription
Input characteristics (Pin 1)
V
IL
, Low-level input voltage
TO Tri-state or power-down
Test conditions
4.5 ~ 5.5 V Vdd
3.0 ~ 3.6 V Vdd
4.5 ~ 5.5 V Vdd
3.0 ~ 3.6 V Vdd
V
IN
= 0V
V
IN
= Vdd
4.5 V ~ 5.5 V Vdd, 16 mA I
OL
3.0 V ~ 3.6 V Vdd, 8 mA I
OL
4.5 V ~ 5.5 V Vdd, -16 mA I
OL
4.5 ~ 5.5 Vdd, -16 mA I
OL
3.0 V ~ 3.6 V Vdd, -8 mA I
OL
4.5 ~ 5.5 Vdd, O
UTPUT FREQ
£
133 MHz
3.0 ~ 3.6 Vdd, O
UTPUT FREQ
£
100 MHz
4.5 ~ 5.5 Vdd, V
IN
= 0V
4.5 ~ 5.5 Vdd, V
IN
= 0.7 V
5.0 Vdd
Output is tri-stated
Output is tri-stated
Min
Typ
Max
0.8
0.2 Vdd
Unit
V
V
V
V
µA
µA
V
V
V
V
V
mA
mA
µA
MÙ
KÙ
µA
V
IH
, High-level input voltage
TO Enable output or no connect
2.0
0.7 Vdd
10
5
0.4
0.4
2.4
Vdd - 0.4
Vdd - 0.4
45
25
50
8.0
200
I
IL
, Input low current
I
IH
, Input high current
Output characteristics
V
OL
, Low-level output voltage
V
OHTTL
, High-level output voltage TTL
V
OHCMOS
High-level CMOS voltage
Power supply current
(unloaded)
Standby current
Input pull-up resistor
(P
IN
1)
Tri-state leakage current
Output enable mode
Power down mode
Output clock switching characteristics
1.1
50
10
3.0
100
20
Description
Duty cycle
TTL @ 1.4 V
4.5 ~ 5.5 Vdd
Test conditions
£
50 MHz, C
L
= 50 pF
50 ~ 66 MHz, C
L
= 15 pF
66 ~ 125 MHz, C
L
= 25 pF
125 ~ 133 MHz, C
L
= 15 pF
£
66 MHz, C
L
£
25 pF
66 ~ 125 MHz, C
L
£
25 pF
125 ~ 133 MHz, C
L
£
15 pF
£
40 MHz, C
L
£
30 pF
40 ~ 100 MHz, C
L
£
15 pF
0.8 V ~ 2.0 V, 4.5 ~ 5.5 Vdd, C
L
= 50
0.8 V ~ 2.0 V, 4.5 ~ 5.5 Vdd, C
L
= 25
0.8 V ~ 2.0 V, 4.5 ~ 5.5 Vdd, C
L
= 15
0.2 ~ 0.8 Vdd, 4.5 ~ 5.5 Vdd, C
L
= 50
0.2 ~ 0.8 Vdd, 3.0 ~ 3.6 Vdd, C
L
= 30
0.2 ~ 0.8 Vdd, 3.0 ~ 3.6 Vdd, C
L
= 15
From power on
PWR_DWN pin LOW to output Hi-Z
Min
45
45
40
40
45
40
40
45
40
Typ
Max
55
55
60
60
55
60
60
55
60
1.8
1.2
0.9
3.4
4.0
2.4
2
Unit
%
%
%
%
%
%
%
%
%
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ps
ps
ps
Duty cycle:
CMOS @ Vdd / 2
4.5 ~ 5.5 Vdd
3.0 ~ 3.6 Vdd
Output clock rise / fall
Start up time
Power down delay time
Synchronous
Asynchronous
Output disable time
Synchronous
Asynchronous
Output enable time
Period Jitter:
Ó
Peak to peak
T/2
10
T/2
10
8
65
65
T+10
15
T+10
15
100
11
99
80
OE pin LOW to output Hi-Z
T = Frequency oscillator period
1 - 133 MHz
£
33.000 MHz
> 33.000 MHz
auris-GmbH
office@auris-gmbh.de www.auris-gmbh.de
All specifications are subject to change without notice.
3.6
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