6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
ICS83056I-01
General Description
The ICS83056I-01 is a 6-bit, 2:1, Single-ended
LVCMOS Multiplexer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The ICS83056I-01 has two
selectable single-ended LVCMOS clock inputs and
six single-ended LVCMOS clock outputs. The outputs have a V
DDO
which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for
use in voltage translation applications. An output enable pin
places the output in a high impedance state which may be useful
for testing or debug. Possible applications include systems with up
to 6 transceivers which need to be independently set for different
rates. For example, a board may have six transceivers, each of
which need to be independently configured for 1 Gigabit Ethernet
or 1 Gigabit Fibre Channel rates. Another possible application may
require the ports to be independently set for FEC (Forward Error
Correction) or non-FEC rates. The device operates up to 250MHz
and is packaged in a 20 TSSOP.
Features
•
•
•
•
6-Bit, 2:1 single-ended LVCMOS multiplexer
Maximum output frequency: 250MHz
Additive phase jitter, RMS at 155.52MHz (12kHz - 20MHz):
0.18ps (typical)
Operating supply modes:
Core/Output
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
ICS
Block Diagram
Q0
•
•
CLK0
Pulldown
0
CLK1
Pulldown
SEL0
Pulldown
1
0
Q1
Pin Assignment
SEL5
Q5
V
DDO
GND
Q4
SEL4
CLK1
V
DD
Q3
SEL3
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SEL0
Q0
V
DDO
GND
Q1
SEL1
CLK0
OE
Q2
SEL2
1
SEL1
Pulldown
0
Q2
1
SEL2
Pulldown
0
Q3
ICS83056I-01
20-Lead TSSOP
6.50mm x 4.40mm x 0.925mm
package body
G Package
Top View
1
SEL3
Pulldown
0
Q4
1
SEL4
Pulldown
0
Q5
1
SEL5
Pulldown
OE
Pullup
IDT™ / ICS™
2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
1
ICS83056AGI-01 REV. A JANUARY 29, 2009
ICS83056I-01
6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 6
10, 11
15, 20
2, 5, 9
12, 16, 19
3, 18
4, 17
7, 14
8
13
Name
SEL5, SEL4,
SEL3, SEL2,
SEL1, SEL0
Q5, Q4, Q3,
Q2, Q1, Q0
V
DDO
GND
CLK1, CLK0
V
DD
OE
Input
Type
Pulldown
Description
Clock select inputs. See Table 3. LVCMOS / LVTTL interface levels.
Output
Power
Power
Input
Power
Input
Pullup
Pulldown
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output supply pins.
Power supply ground.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Power supply pin.
Output enable. When LOW, outputs are in a High impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
V
DD
= V
DDO
= 3.465V
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
V
DDO
= 3.465V
Output Impedance
V
DDO
= 2.625V
V
DDO
= 2V
V
DD
= V
DDO
= 2.625V
V
DD
= V
DDO
= 2V
Test Conditions
Minimum
Typical
4
18
19
19
51
51
15
17
25
Maximum
Units
pF
pF
pF
pF
k
Ω
k
Ω
Ω
Ω
Ω
Function Tables
Table 3. Control Input Function Table
Control Inputs
SELx
0
1
Outputs
Qx
CLK0
CLK1
IDT™ / ICS™
2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
2
ICS83056AGI-01 REV. A JANUARY 29, 2009
ICS83056I-01
6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
91.1°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V±5%, V
DDO
= 3.3V ± 5% or 2.5V±5%, or 1.8V±0.2V,
T
A
= -40°C to 85°C
Symbol
V
DD
Parameter
Positive Supply Voltage
Test Conditions
Minimum
3.135
3.135
V
DDO
Output Supply Voltage
2.375
1.6
I
DD
I
DDO
Power Supply Current
Output Supply Current
No Load
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
2.0
45
5
Units
V
V
V
V
mA
mA
Table 4B. Power Supply DC Characteristics,
V
DD
= 2.5V±5%, V
DDO
= 2.5V±5% or 1.8V±0.2V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
1.6
Power Supply Current
Output Supply Current
No Load
1.8
2.0
40
5
V
mA
mA
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
Units
V
V
IDT™ / ICS™
2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
3
ICS83056AGI-01 REV. A JANUARY 29, 2009
ICS83056I-01
6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
Table 4C. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
Input Low Voltage
CLK0, CLK1,
SEL[0:5]
OE
Input
Low Current
CLK0, CLK1,
SEL[0:5]
OE
V
DD
= 3.465V
V
DD
= 2.625V
Input
High Current
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DDO
= 3.3V ± 5%, I
OH
= -24mA
V
OH
Output High Voltage;
V
DDO
= 2.5V ± 5%, I
OH
= -12mA
V
DDO
= 1.8V ± 0.2V, I
OH
= -4mA
V
DDO
= 3.3V ± 5%, I
OL
= 24mA
V
OL
Output Low Voltage
V
DDO
= 2.5V ± 5%, I
OL
= 12mA
V
DDO
= 1.8V ± 0.2V, I
OL
= 4mA
-5
-150
2.6
1.8
V
DDO
- 0.3
0.5
0.45
0.35
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
1.3
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
V
V
IL
I
IH
I
IL
IDT™ / ICS™
2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
4
ICS83056AGI-01 REV. A JANUARY 29, 2009
ICS83056I-01
6-BIT, 2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
tp
LH
tp
HL
tjit
tsk(i)
tsk(o)
tsk(pp)
t
R
/ t
F
odc
MUX
ISOLATION
Parameter
Output Frequency
Propagation Delay, Low-to-High;
NOTE 1
Propagation Delay, High-to-Low;
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 2
Input Skew; NOTE 3
Output Skew: NOTE 4
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
20% to 80%
f
OUT
≤
175MHz
100MHz
300
40
45
155.52MHz, Integration Range:
12kHz – 20MHz
1.8
2.0
2.5
2.6
Test Conditions
Minimum
Typical
Maximum
250
3.2
3.2
Units
MHz
ns
ns
0.18
145
130
800
800
60
ps
ps
ps
ps
ps
%
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Driving only one input clock.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Table 5B. AC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
tp
LH
tp
HL
tjit
tsk(i)
tsk(o)
tsk(pp)
t
R
/ t
F
odc
MUX
ISOLATION
Parameter
Output Frequency
Propagation Delay, Low-to-High;
NOTE 1
Propagation Delay, High-to-Low;
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section;
NOTE 2
Input Skew; NOTE 3
Output Skew: NOTE 4
Part-to-Part Skew; NOTE 3, 5
Output Rise/Fall Time
Output Duty Cycle
MUX Isolation
100MHz
20% to 80%
300
40
45
155.52MHz, Integration Range:
12kHz – 20MHz
2.1
2.3
2.6
2.7
Test Conditions
Minimum
Typical
Maximum
250
3.1
3.1
Units
MHz
ns
ns
0.14
100
130
800
800
60
ps
ps
ps
ps
ps
%
dB
See notes in Table 5A above.
IDT™ / ICS™
2:1, SINGLE-ENDED LVCMOS MULTIPLEXER
5
ICS83056AGI-01 REV. A JANUARY 29, 2009
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