CAT5419
Dual Digitally Programmable Potentiometers (DPP™)
with 64 Taps and 2-wire Interface
FEATURES
Two linear-taper digital potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
Potentiometer control and memory access via
2-wire Interface (I
2
C like)
Low wiper resistance, typically 80
Four non-volatile wiper settings for each
potentiometer
Recall of wiper settings at power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Write protection for data register
DESCRIPTION
The CAT5419 is two Digitally Programmable
Potentiometers (DPP™) integrated with control logic
and 16 bytes of NVRAM memory.
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DPP.
Associated with each wiper control register are four 6-
bit non-volatile memory data registers (DR) used for
storing up to four wiper settings. Writing to the wiper
control register or any of the non-volatile data regis-
ters is via a 2-wire serial bus (I
2
C-like). On power-up,
the contents of the first data register (DR0) for each of
the two potentiometers is automatically loaded into its
respective wiper control registers (WCR).
¯¯¯
The Write Protection (WP) pin protects against
inadvertent programming of the data register.
The CAT5419 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC (W)
(top view)
V
CC
R
L0
R
H0
R
W0
A2
¯¯¯
WP
SDA
A
1
R
L1
R
H1
R
W1
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
NC
NC
NC
NC
A
0
NC
A
3
SCL
NC
NC
NC
NC
SDA
A
1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCL
A
3
For Ordering Information details, see page 15.
TSSOP (Y)
(top view)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
¯¯¯
WP
A
2
R
W0
R
H0
R
L0
V
CC
NC
NC
NC
NC
A
0
NC
R
L0
R
L1
A0
A1
A2
A3
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
WP
R
W1
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
FUNCTIONAL DIAGRAM
R
H0
R
H1
R
W0
CAT
19
5419
18
17
16
15
14
13
CAT
19
5419
18
17
16
15
14
13
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2115 Rev. H
CAT5419
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT5419 serial clock input pin is used to
clock all data transfers into or out of the device.
SDA:
Serial Data
The CAT5419 bidirectional serial data pin is used
to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-
OR'd with the other open drain or open collector
outputs.
A0, A1, A2, A3:
Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with the
address input in order to initiate communication
with the CAT5419.
R
H
, R
L
:
Resistor End Points
The R
H
and R
L
pins are equivalent to the terminal
connections on a mechanical potentiometer.
R
W
:
Wiper
The R
W
pins are equivalent to the wiper terminal of
a mechanical potentiometer.
¯¯¯:
Write Protect Input
WP
The ¯¯¯ pin when tied low prevents non-volatile
WP
writes to the data registers (change of wiper
control register is allowed) and when tied high or
left floating normal read/write operations are
allowed. See page 7, Write Protection for more
details.
Pin
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin
TSSOP
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
V
CC
R
L0
R
H0
R
W0
A2
¯¯¯
WP
SDA
A1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCL
A3
NC
A0
NC
NC
NC
NC
Function
Supply Voltage
Low Reference Terminal for
Potentiometer 0
High Reference Terminal for
Potentiometer 0
Wiper Terminal for
Potentiometer 0
Device Address
Write Protection
Serial Data Input/Output
Device Address
Low Reference Terminal for
Potentiometer 1
High Reference Terminal for
Potentiometer 1
Wiper Terminal for
Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Device Address
No Connect
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
DEVICE OPERATION
The CAT5419 is two resistor arrays integrated with 2wire serial interface logic, four 6-bit wiper control registers
and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
). R
H
and R
L
are symmetrical and may be interchanged. The tap positions between and
at the ends of the series resistors are connected to the output wiper terminals (R
W
) by a CMOS transistor switch.
Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile
memory data registers via the 2-wire bus. Additional instructions allow data to be transferred between the wiper
control registers and each respective potentiometer's non-volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement" mode.
Doc. No. MD-2115 Rev. H
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5419
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Temperature Under Bias
Storage Temperature Range
Voltage to any Pins with Respect to V
SS (2) (3)
V
CC
with Respect to GND
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Wiper Current
RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
Ratings
+2.5 to 6.0
-40 to +85
Units
V
ºC
Ratings
-55 to +125
-65 to +150
-2.0 to V
CC
+2.0
-2.0 to +7.0
1.0
300
±12
Units
ºC
ºC
V
V
W
ºC
mA
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
R
POT
R
POT
R
POT
R
POT
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance Tolerance
R
POT
Matching
Power Rating
I
W
R
W
R
W
V
TERM
V
N
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Noise
Resolution
Absolute Linearity
(5)
Relative Linearity
(6)
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
R
W(n)(actual)
-R
(n)(expected)(8)
R
W(n+1)
-[R
W(n)+LSB
]
(8)
(4)
(4)
(4)
Test Conditions
Min
Typ
100
50
10
2.5
Max
Units
kΩ
kΩ
kΩ
kΩ
±20
1
25°C, each pot
I
W
= ±3mA @ V
CC
= 3V
I
W
= ±3mA @ V
CC
= 5V
V
SS
= 0V
(4)
%
%
mW
mA
Ω
Ω
V
nV/√Hz
%
50
±6
300
80
GND
TBD
1.6
±1
±0.2
±300
20
10/10/25
0.4
150
V
CC
LSB
(7)
LSB
(7)
ppm/°C
ppm/°C
pF
MHz
R
POT
= 50kΩ
(4)
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(7) LSB = R
TOT
/ 63 or (R
H
- R
L
) / 63, single pot
(8) n = 0, 1, 2, ..., 63
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2115 Rev. H
CAT5419
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
I
OL
= 3 mA
Test Conditions
f
SCL
= 400kHz
V
IN
= GND or V
CC
; SDA Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
Min
Max
1
1
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
µA
µA
µA
V
V
V
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
= 25˚C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted).
Symbol
C
I/O
C
IN
Test Conditions
Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, ¯¯¯)
WP
Min
Typ
Max
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
f
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
50
1.2
0.6
1.2
0.6
0.6
0
100
0.3
300
Min
Typ
Max
400
50
0.9
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
POWER UP TIMING
(1)
Over recommended operating conditions unless otherwise stated.
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2115 Rev. H
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5419
WRITE CYCLES LIMITS
Symbol
t
WR
Parameter
Write Cycle Time
Max
5
Units
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
N
END
(1)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
T
DR(1)
V
ZAP(1)
I
LTH(1)(2)
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
SDA IN
tAA
SDA OUT
tDH
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-2115 Rev. H
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