VCXO and Synchronous Ethernet
Jitter Attenuator
Data Sheet
810252I
General Description
The 810252I is a high performance, low jitter/low phase noise
VCXO. The 810252I uses a low frequency and low cost pullable
crystal to achieve jitter attenuation for synchronous Ethernet
applications. The 810252I can take an input of 25MHz and produce
two LVCMOS outputs of 25MHz.
The device is packaged in a small 16 lead TSSOP package and is
ideal for use on space constrained boards typically encountered in
most synchronous ethernet applications.
Features
•
•
•
•
•
•
•
•
Two single-ended outputs (LVCMOS or LVTTL levels),
output Impedance: 15
Phase jitter attenuation by the VCXO-PLL using a 25MHz pullable
external crystal (XTAL)
Input frequencies: 25MHz or 125MHz
Output frequency: 25MHz
PLL loop bandwidth adjustable by external components
Full 3.3V or 2.5V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Applications
•
•
Synchronous Ethernet v0.39a
End equipment compliant with Std IEEE 802.039a
Block Diagram
XTAL_OUT
XTAL_IN
Pin Assignment
PLL_SEL
GND
Q0
PLL_SEL
Pullup
(External Loop Filter Inputs)
LF1
LF0
OE
Pullup
Q1
V
DDO
OE
V
DDA
V
DD
Q0
25MHz
(25MHz or 125MHz
Input Frequency Auto Detect)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK_IN
V
DD
LF1
LF0
GND
XTAL_IN
XTAL_OUT
GND
CLK_IN
Pulldown
Pre-
Divider
(÷1 or ÷5)
PFD
CP
VCXO-PLL
810252I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
VCXO
1
25MHz
0
Q1
©2016 Integrated Device Technology, Inc
1
Revision B March 3, 2016
810252I Data Sheet
Table 1. Pin Descriptions
Number
1
2, 9, 12
3, 4
5
6
7
8, 15
10,
11
13, 14
16
Name
PLL_SEL
GND
Q0, Q1
V
DDO
OE
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
LF0, LF1
CLK_IN
Input
Power
Output
Power
Input
Power
Power
Input
Analog
Input/
Output
Input
Pulldown
Pullup
Type
Pullup
Description
When logic HIGH, the VCXO-PLL is enabled. When LOW, the VCXO-PLL is in
bypass mode. LVCMOS/LVTTL interface levels.
Power supply ground.
Single-ended clock outputs. LVCMOS/ LVTTL interface levels.
Output power supply pin.
Output enable pin for Qx outputs. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pins.
VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Loop filter connection node pins.
Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
V
DD,
V
DDO
= 3.465V
V
DD,
V
DDO
= 2.625V
Test Conditions
Minimum
Typical
4
8
5
51
51
V
DDO
= 3.3V±5%
V
DDO
= 2.5V±5%
15
20
Maximum
Units
pF
pF
pF
k
k
R
PULLDOWN
Input Pulldown Resistor
R
OUT
Output Impedance
©2016 Integrated Device Technology, Inc
2
Revision B March 3, 2016
810252I Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
81.2C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
3.135
V
DD
– 0.07
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
40
7
5
Units
V
V
V
mA
mA
mA
Table 3B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
No Load
Test Conditions
Minimum
2.375
V
DD
– 0.07
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
DD
2.625
35
7
5
Units
V
V
V
mA
mA
mA
©2016 Integrated Device Technology, Inc
3
Revision B March 3, 2016
810252I Data Sheet
Table 3C. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
CLK_IN
OE, PLL_SEL
CLK_IN
OE, PLL_SEL
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
DDO
= 2.5V ± 5%
Output Low Voltage; NOTE 1
V
DDO
= 3.3V ± 5%
V
DDO
= 2.5V ± 5%
-5
-150
2.6
1.8
0.6
0.5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
V
IL
I
IH
I
IL
V
OH
Output High Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
to V
DDO
/2. See Parameter Measurement Information section.
Load Test Circuit diagrams.
AC Electrical Characteristics
Table 4A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
REF
f
VCO
f
OUT
t
JIT(CC)
tsk(o)
tjit()
t
JIT(PER)
t
R
/ t
F
odc
odc
Parameter
Input Reference Frequency
VCXO-PLL Frequency
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
Output Skew; NOTE 2, 3
RMS Phase Jitter (Random);
NOTE 4
Period Jitter, RMS
Output Rise/Fall Time
Output Duty Cycle; NOTE 5
Output Duty Cycle; NOTE 6
20% to 80%
550
48
45
f
OUT
= 25MHz, Integration Range:
12kHz – 5MHz
0.25
2.7
1100
52
55
Test Conditions
Minimum
Typical
25
125
25
25
25
15
Maximum
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using a 537Hz VCXO-PLL Loop Bandwidth. Refer to VCXO_PLL Applications Section.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Refer to the Phase Noise Plot.
NOTE 5: Specified with the VCXO-PLL free running high.
NOTE 6: Specified with the VCXO-PLL locked.
©2016 Integrated Device Technology, Inc
4
Revision B March 3, 2016
810252I Data Sheet
Table 4B. AC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
REF
f
VCO
f
OUT
t
JIT(CC)
tsk(o)
tjit
t
JIT(PER)
t
R
/ t
F
odc
odc
Parameter
Input Reference Frequency
VCXO-PLL Frequency
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
Output Skew; NOTE 2, 3
RMS Phase Jitter (Random);
NOTE 4
Period Jitter, RMS
Output Rise/Fall Time
Output Duty Cycle; NOTE 5
Output Duty Cycle; NOTE 6
20% to 80%
700
48
44
f
OUT
= 25MHz, Integration Range:
12kHz – 5MHz
0.26
5.7
1850
52
56
Test Conditions
Minimum
Typical
25
125
25
25
20
25
Maximum
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using a 537Hz VCXO-PLL Loop Bandwidth. Refer to VCXO_PLL Applications Section.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Refer to the Phase Noise Plot.
NOTE 5: Specified with the VCXO-PLL free running high.
NOTE 6: Specified with the VCXO-PLL locked.
©2016 Integrated Device Technology, Inc
5
Revision B March 3, 2016
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