18Mb Pipelined
DDR™II SRAM
Burst of 4
Features
◆
◆
◆
◆
◆
IDT71P73204
IDT71P73104
IDT71P73804
IDT71P73604
Description
The IDT DDRII
TM
Burst of four SRAMs are high-speed synchro-
nous memories with a double-data-rate (DDR), bidirectional data port.
This scheme allows maximization on the bandwidth on the data bus by
passing two data items per clock cycle. The address bus operates at
less than single data rate speeds,allowing the user to fan out addresses
and ease system design while maintaining maximum performance on
data transfers.
The DDRII has scalable output impedance on its data output bus
and echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds
beyond SRAM devices that use any form of TTL interface. The inter-
face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a V
DDQ
and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V V
DD.
The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
◆
◆
◆
◆
◆
◆
◆
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)
Common Read and Write Data Port
Dual Echo Clock Output
4-Word Burst on all SRAM accesses
Multiplexed Address Bus
-
One Read or One Write request per two clock
cycles.
DDR (Double Data Rate) Data Bus
- Four word bursts data per two clock cycles
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
-
Output Impedance adjustable from 35 ohms to 70
ohms
1.8V Core Voltage (V
DD
)
JTAG Interface
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
Functional Block Diagram
DATA
REG
(Note1)
WRITE DRIVER
LD
RW
BWx
(Note3)
CTRL
LOGIC
18M
MEMORY
ARRAY
(Note4)
OUTPUT SELECT
SENSE AMPS
OUTPUT REG
SA
SA
0
SA
1
ADD
REG
(Note2)
WRITE/READ DECODE
(Note2)
(Note4)
(Note1)
DQ
K
K
C
C
CLK
GEN
SELECT OUTPUT CONTROL
6431 drw 16
CQ
CQ
Notes
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x8 and x9, 20 address signal lines for x18, and 19 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the
BW
is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
JULY 2005
1
©2005 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.“
DSC-6431/00
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Clocking
The DDRII SRAM has two sets of input clocks, namely the K,
K
clocks and the C,
C
clocks. In addition, the QDRII has an output “echo”
clock, CQ,
CQ.
The K and
K
clocks are the primary device input clocks. The K
clock is used to clock in the control signals (LD, R/W and
BWx
or
NWx),
the address, and the first and third words of the data burst during a write
operation. The
K
clock is used to clock in the control signals (BWx or
NWx),
and the second and fourth words of the data burst during a write
operation. The K and
K
clocks are also used internally by the SRAM. In
the event that the user disables the C and
C
clocks, the K and
K
clocks
will also be used to clock the data out of the output register and generate
the echo clocks.
The C and
C
clocks may be used to clock the data out of the
output register during read operations and to generate the echo clocks.
C and
C
must be presented to the SRAM within the timing tolerances.
The output data from the DDRII will be closely aligned to the C and
C
input, through the use of an internal DLL. When C is presented to the
DDRII SRAM, the DLL will have already internally clocked the data to
arrive at the device output simultaneously with the arrival of the
C
clock.
The C and second data item of the burst will also correspond. The third
and fourth data words will follow on the next clock cycle of the
C
and C,
respectively.
Single Clock Mode
The DDRII SRAM may be operated with a single clock pair. C
and
C
may be disabled by tying both signals high, forcing the outputs
and echo clocks to be controlled instead by the K and
K
clocks.
DLL Operation
The DLL in the output structure of the DDRII SRAM can be used
to closely align the incoming clocks C and
C
with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLL by holding
Doff
low. With the DLL off, the C and
C
(or K and
K
if C and
C
are not used) will directly clock the output register of the
SRAM. With the DLL off, there will be a propagation delay from the time
the clock enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ and
CQ,
are generated by the C and
C
clocks (or K,
K
if C,
C
are disabled). The rising edge of C generates the
rising edge of CQ, and the falling edge of
CQ.
The rising edge of
C
generates the rising edge of
CQ
and the falling edge of CQ. This
scheme improves the correlation of the rising and falling edges of the
echo clock and will improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guarantee-
ing that the echo clock will remain closely correlated with the data, within
the tolerances designated.
Read and Write Operations
Read operations are initiated by holding Read/Write control input
(R/W) high, the load control input (LD) low and presenting the read
address to the address port during the rising edge of K, which will latch
the address. The data will then be read and will appear at the device
output at the designated time in correspondence with the C and
C
clocks.
Write operations are initiated by holding the Read/Write control
input (R/W) low, the load control input (LD) low and presenting the write
address to the address port during the rising edge of K, which will latch
the address. On the following rising edge of K, the first word of the four
word burst must be present on the data input bus DQ[x:O], along with the
appropriate byte write or nibble write (BWx or
NWx)
inputs. On the
following rising edge of
K,
the second word of the data write burst will be
accepted at the device input with the designated (BWx or
NWx)
inputs.
The subsequent K and
K
rising edges will receive the last two words of
the four word burst, with their
BWx/NWx
enables.
DDRII devices internally store four words of the burst as a single,
wide word and will retain their order in the burst. The x8 and x9 devices
do not have the ability to address to the single word level or change the
burst order; however the byte and nibble write signals can be used to
prevent writing any byte or individual nibbles, or combined to prevent
writing one word of the burst. The x18 and x36 DDRll devices have the
ability to address to the individual word level using the SA
0
and SA
1
address bits, but the burst will continue in a linear sequence and wraps
around without incrementing the SA bits. When reading or writing x18
and x36 DDRll devices, the burst will begin at the designated address,
but if the burst is started at any other position than the first word of the
burst, the burst will wrap back on itself and read the first locations before
completing. The x18 and x36 DDRII devices can also use the byte write
signals to prevent writing any individual byte or word of the burst.
Output Enables
The DDRII SRAM automatically enables and disables the DQ[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the DQ outputs will come up in a high impedance
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and Vss to allow the SRAM to adjust its output drive
impedance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with V
DDQ
= 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to V
DDQ
.
6.42
2
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Definitions
Symbol
Pin Function
Description
Data I/O signals. Data inputs are sampled on the rising edge of K and
K
during valid write operations. Data outputs are driven
during a valid read operation. The outputs are aligned with the rising edge of both C and
C
during normal operation. When
operating in a single clock mode (C and
C
tied high), the outputs are aligned with the rising edge of both K and
K.
When a
Read operation is not initiated or
LD
is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high
impedance after any previous read operation in progress completes.
2M x 8 -- DQ[7:0]
2M x 9 -- DQ[8:0]
1M x 18 -- DQ[17:0]
512K x 36 -- DQ[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of
K
clocks
during write operations. Used to select which byte is written into the device during the current portion of the write operations.
Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written in to the device.
2M x 9 --
BW
0
controls DQ[8:0]
1M x 18 --
BW
0
controls DQ[8:0] and
BW
1
controls DQ[17:9]
512K x 36 --
BW
0
controls DQ[8:0],
BW
1
controls DQ[17:9],
BW
2
controls DQ[26:18] and
BW
3
controls DQ[35:27]
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising
edge of the K and
K
clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered. All the nibble writes are sampled on the same edge as the
data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written in to the
device.
2M x 8 --
NW0
controls D[3:0] and
NW1
controls D[7:4].
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
Burst count address bits on x18 and x36 DDRll devices. These bits allow changing the burst order in read or write operations, or
addressing to the individual word of a burst. See page 9 for all possible burst sequences.
Load Control Logic. Sampled on the rising edge of K. If
LD
is low, a four word burst read or write operation will initiate
designated by the R/W input. If
LD
is high during the rising edge of K, operations in progress will complete, but new operations
will not be initiated.
Read or Write Control Logic. If
LD
is low during the rising edge of K, the R/W indicates whether a new operation should be a
read or write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the
LD
input is
high during the rising edge of K, the R/W input will be ignored.
Positive Output Clock Input. C is used in conjunction with
C
to clock out the Read data from the device. C and
C
can be used
together to deskew the flight times of various devices on the board back to the controller. See application example for further
details.
Negative Output Clock Input.
C
is used in conjunction with C to clock out the Read data from the device. C and
C
can be used
together to deskew the flight times of various devices on the board back to the controller. See application example for further
details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data
through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
Negative Input Clock Input.
K
is used to capture synchronous inputs being presented to the device and to drive out data through
DQ[X:0] when in single clock mode.
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can
be used as a data valid indication. These signals are free running and do not stop when the output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. DQ[X:0]
output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
6431 tbl 02a
DQ[X:0]
Input/Output
Synchronous
BW
0
,
BW
1
BW
2
,
BW
3
Input
Synchronous
NW0, NW1
Input
Synchronous
SA
SA
0
, SA
1
Input
Synchronous
Input
Synchronous
Input
Synchronous
LD
R/W
Input
Synchronous
C
Input Clock
C
Input Clock
K
K
CQ,
CQ
Input Clock
Input Clock
Output Clock
ZQ
Input
6.42
3
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Definitions continued
Symbol
Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL
turned off will be different from those listed in this data sheet. There will be an increased propagation
delay from the incidence of C and
C
to DQ, or K and
K
to DQ as configured. The propagation delay is not
a tested parameter, but will be similar to the propagation delay of other SRAM devices in this speed
grade.
TDO pin for JTAG
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to V
DD
when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to V
DD
when the pin is unconnected.
No connects inside the package. Can be tied to any voltage level
Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs as well
as AC measurement points.
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground for the device. Should be connected to ground of the system.
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or
scaled to the desired output voltage.
6431 tbl 02b
Doff
Input
TDO
TCK
TDI
TMS
NC
V
REF
V
DD
V
SS
V
DDQ
Output
Input
Input
Input
No
Connect
Input
Reference
Power
Supply
Ground
Power
Supply
6.42
4
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 4
Commercial Temperature Range
Pin Configuration IDT71P73204 (2M x 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
V
SS/
SA
(2)
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ
6
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ
4
NC
DQ
5
V
DDQ
NC
NC
NC
NC
NC
DQ
7
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NW
1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
NW
0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
V
SS/
SA
(1)
NC
NC
NC
NC
NC
NC
V
REF
DQ
1
NC
NC
NC
NC
NC
TMS
6431 tbl 12
11
CQ
DQ
3
NC
NC
DQ
2
NC
NC
ZQ
NC
NC
DQ
0
NC
NC
NC
TDI
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A10 is reserved for the 36Mb expansion address.
2. A2 is reserved for the 72Mb expansion address.
6.42
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
