Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
The device contains two internal PLL stages that are cascaded
in series. The first PLL stage attenuates the reference clock jitter
by using an internal or external VCXO circuit. The internal VCXO
requires the connection of an external inexpensive pullable
crystal (XTAL) to the ICS813076I. This first PLL stage (VCXO
PLL) uses external passive loop filter components which are used
to optimize the PLL loop bandwidth and damping characteristics
for the given application. The output of the first stage VCXO PLL
is a stable and jitter-tolerant reference input for the second PLL
stage of 30.72MHz. The second PLL stage provides frequency
translation by multiplying the output of the first stage up to
614.4MHz. The low phase noise characteristics of the clock
signal is maintained by the internal FemtoClock™ PLL, which
requires no exter nal components or configuration. Two
independently configurable frequency dividers translate the
491.52MHz or 614.4MHz internal VCO signal to the desired output
frequencies. All frequency translation ratios are set by device
configuration pins. Alternative to the clock frequency multiplication
functionality, the ICS813076I can work as a VCXO. Enabling the
VCXO mode allows the output frequency of 614.4/N or 491.52/N
MHz to be pulled by the input voltage of the VC pin.
•
Supported input reference clock frequencies:
15.36MHz,
30.72MHz
61.44MHz
•
Supported output clock frequencies:
30.72MHz
122.88MHz
153.6MHz
491.52MHz
614.4MHz
P
IN
A
SSIGNMENT
LF1
LF0
ISET
VC
FLM
V
CC
V
CC
CLK1
nCLK1
nMR
CLK0
nCLK0
V
EE
LOCK
V
CCO
NA1
64 63 62 6160 59 58 57 56 55 54 53 52 51 50 49
48
1
2
47
3
46
45
4
5
44
43
6
64-Lead TQFP, E-Pad
42
7
10mm x 10mm x 1.0mm
8
41
9
40
package body
39
10
Y package
38
11
Top View
37
12
13
36
35
14
34
15
33
16
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
nQA0
QA0
V
CC
nQC0
QC0
V
CCO
V
EE
nc
nc
MF
MV
VC_SEL
V
CC
XTAL_OUT
XTAL_IN
V
EE
ICS813076I
nQA1
QA1
V
CCO
nQA2
QA2
V
EE
nQA3
QA3
V
CCO
nQA4
QA4
V
CC
V
EE
nQB0
QB0
V
CCO
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
nQB1
QB1
V
CCO
nQB2
QB2
V
CCA
nc
REF_SEL
nSTOP
nBYPASS
P
NC0
NC1
NB0
NB1
NA0
IDT
™
/ ICS
™
FREQUENCY GENERATOR/JITTER ATTENUATION
1
ICS813076BYI REV. A AUGUST 17, 2007
ICS813076I
FREQUENCY GENERATOR/JITTER ATTENUATION FOR WIRELESS INFRASTRUCTURE
PRELIMINARY
B
LOCK
D
IAGRAM
30.72MHz
XTAL_IN
XTAL_OUT
ISET
LF0
LF1
LOCK
QA0
÷NA
nQA0
QA4
nQA4
f
PD
Pulldown
Pullup/Pulldown
Pulldown
Pullup/Pulldown
f
VCXO
f
VCO
0
CLK0
nCLK0
CLK1
nCLK1
P
VC
VC_SEL
Pulldown
QB0
÷NB
0
1
÷P
PD
CP
VCXO
Femto
PLL
nQB0
QB1
nQB1
QB2
1
Pulldown
÷MF
nQB2
Multiplier / Divider
÷NC
÷MV
Internal VCXO
QC0
nQC0
MV
MF
REF_SEL
nBYPASS
NA[1:0]
NB[1:0]
NC[1:0]
FLM
nMR
nSTOP
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
IDT
™
/ ICS
™
FREQUENCY GENERATOR/JITTER ATTENUATION
2
ICS813076BYI REV. A AUGUST 17, 2007
ICS813076I
FREQUENCY GENERATOR/JITTER ATTENUATION FOR WIRELESS INFRASTRUCTURE
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3
4
5
6, 7, 37,
51, 61
8
9
10
11
12
13, 36, 43,
55, 64
14
15, 30, 33,
40, 46, 54
16, 17
18, 19
20, 21
22
23
24
25
26, 56, 57
27
28, 29
3 1, 3 2
3 4, 35
38, 39
41, 4 2
4 4, 45
4 7 , 48
49, 50
52, 53
58
59
Name
LF1, LF0
ISET
VC
FLM
V
CC
CLK1
nCLK1
nMR
CLK0
nCLK0
V
EE
LOCK
V
CCO
NA1, NA0
NB1, NB0
NC1, NC0
P
nBYPASS
nSTOP
REF_SEL
nc
V
CCA
QB2, nQB2
QB1, nQB1
QB0, nQB0
QA4, nQA4
QA3, nQA3
QA2, nQA2
QA1, nQA1
nQA0, QA0
nQC0, QC0
MF
MV
Analog
Analog
Analog
Input
Power
Input
Input
Input
Input
Input
Power
Output
Power
Input
Input
Input
Input
Input
Input
Input
Unused
Power
Output
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pullup/
Pulldown
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
External loop filter.
Charge pump current setting.
Control voltage to the VCXO.
VCXO-PLL fast lock mode. LVCMOS/LVTTL interface levels. See Table 3H.
工作这点儿事
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
