FINAL
COM’L: -7/10/12/15/20, Q-12/15/20
IND: -12/14/18/24
MACH210A-7/10/12
MACH210-12/15/20
MACH210AQ-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
44 Pins
64 Macrocells
7.5 ns t
PD
Commercial
12 ns t
PD
Industrial
133 MHz f
CNT
38 Inputs; 210A Inputs have built-in pull-up
resistors
Advanced
Micro
Devices
Peripheral Component Interconnect (PCI)
compliant
32 Outputs
64 Flip-flops; 2 clock choices
4 “PAL22V16” blocks with buried macrocells
Pin-compatible with MACH110, MACH111,
MACH211, and MACH215
GENERAL DESCRIPTION
The MACH210 is a member of AMD’s high-performance
EE CMOS MACH 2 device family. This device has
approximately six times the logic macrocell capability of
the popular PAL22V10 without loss of speed.
The MACH210 consists of four PAL blocks intercon-
nected by a programmable switch matrix. The four PAL
blocks are essentially “PAL22V16” structures complete
with product-term arrays and programmable macro-
cells, including additional buried macrocells. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity
between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH210 has two kinds of macrocell: output and
buried. The MACH210 output macrocell provides regis-
tered, latched, or combinatorial outputs with program-
mable polarity. If a registered configuration is chosen,
the register can be configured as D-type or T-type to
help reduce the number of product terms. The register
type decision can be made by the designer or by the
software. All output macrocells can be connected to an
I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACH210 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers or latches for use in
synchronizing signals and reducing setup time require-
ments.
Publication#
14128
Rev.
I
Issue Date:
May 1995
Amendment
/0
AMD
ORDERING INFORMATION
Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
MACH
210A -7
J
C
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
DEVICE NUMBER
210
= 64 Macrocells, 44 Pins
210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors
210AQ = 64 Macrocells, 44 Pins, Input Pull-Up Resistors,
Quarter Power
SPEED
-7 = 7.5 ns t
PD
-10 = 10 ns t
PD
-12 = 12 ns t
PD
-15 = 15 ns t
PD
-20 = 20 ns t
PD
Valid Combinations
MACH210A-7
MACH210A-10
MACH210A-12
MACH210-12
MACH210-15
MACH210-20
MACH210AQ-12
MACH210AQ-15
MACH210AQ-20
JC,
VC
OPTIONAL PROCESSING
Blank = Standard Processing
OPERATING CONDITIONS
C = Commercial (0
°
C to +70
°
C)
PACKAGE TYPE
J = 44-Pin Plastic Leaded Chip
Carrier (PL 044)
V = 44-Pin Thin Quad Flat Pack
(PQT044)
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device. Con-
sult the local AMD sales office to confirm availability of
specific valid combinations or to check on newly re-
leased combinations.
JC
MACH210-7/10/12/15/20, Q-12/15/20 (Com’l)
5
FPGA/CPLD
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