80486DX4RP
R
ADIATION
H
ARDENED
--Preliminary--
32-B
IT
M
ICROPROCESSOR
SEi
80486DX4RP
F
EATURES
:
·
32-Bit Microprocessor
·
Total Dose Hardness: typical 100 Krad (Si); dependent upon
orbit
·
Single Event Effect
- SEL
TH
= 40 MeV/mg/cm
2
- SEU
TH
= 5 MeV/mg/cm
2
·
Package:
- 208 Pin R
AD
-P
AK
® Quad Flat Pack
·
8-Kilobyte On-Chip Cache with Consistency Support
·
External Cache Controller
·
Integrated Floating-Point Unit
·
Single Cycle Execution
·
32-Bit RISC Integer Core
·
Instruction Pipelining
·
On-Chip Management Unit
·
Write Buffers
·
Bus Backoff
·
Instruction Restart
·
On Chip Floating Point Unit
D
ESCRIPTION
:
Space Electronics’ 80486DX4RP (RP for R
AD
-P
AK
®) high-performance 32-bit
microprocessor features a typical 100krad (Si) total dose tolerance. The
80486DX4RP processor integrates an 8K unified cache and floating-point (FPU)
hardware-on-chip. The on-chip memory management unit is completely
compatible with the 80386 processor. The 16-kilobyte on-chip cache memory
allows storing of frequently used data and code on-chip, reducing accesses to the
external bus. Its speed-multiplying technology allows the processor to operate at
frequencies higher than the external memory bus. The clock multiplier on the
80486DX4RP improves execution performance without increasing board design
complexity and the Write-Back Enhanced processors are capable of using an on-
chip write-back cache policy. It enhances all operations operating out of the
cache and/or not blocked by external bus accesses. The burst bus feature enables
fast cache fills. The patented radiation-hardened R
AD
-P
AK
® technology
incorporates radiation shielding in the microcircuit package. It provides a 100
krad or better (Si) total dose survivability, based on a GEO-type orbit. Actual TID
tolerance is dependent upon orbit and mission duration. Capable of surviving in
space environment, the 80486DX4 is ideal for satellite, spacecraft, and space
probe missions. It is available in Class S packaging and screening.
0507.98Rev0
Specification and design are subject to change without notice.
1
--4.3--
©1998 Space Electronics Inc.
All rights reserved
80486DX4RP
R
ADIATION
H
ARDENED
32-B
IT
M
ICROPROCESSOR
UNIT
V
V
°
C
°
C
80486DX4RP ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
Supply Voltage with Respect to
V
CC
-0.5
+6.5
Ground
DC Voltage on Other Pins with
-0.5
V
CC
+ 0.5
Respect to Ground
Operating Temperature Range
T
OPR
0
+85
Storage Temperature Range
T
STG
-65
+150
80486DX4RP OPERATING CONDITIONS
SYMBOL
MIN
V
CC
4.5
T
A
0
PARAMETER
Digital Supply Voltage
Temperature Range
MAX
5.5
+80
UNIT
V
°
C
80486DX4RP DC ELECTRICAL CHARACTERISTICS FOR READ OPERATION
(V
CC
=3.3V+0.3, T
A
= 0
°
C to +85
°
C, unless otherwise specified)
PARAMETER
Input Leakage Current
TEST CONDITION
Inputs without Pull-ups or
pull-downs and
0V < V
IN
< V
CC
3/
3/
1/
2/
SYMBOL
I
LI
MIN
-15
TYP
MAX
+15
UNIT
µ
A
µ
A
mA
mA
µ
A
µ
A
V
V
V
V
1450
1100
1300
975
100
75
1000
12
10
14
mA
mA
mA
µ
A
pF
pF
pF
Output Leakage Current
UP# Active Supply Current
Input Leakage Current
Input Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
CC
Active (Power Supply)
6/
I
CC
Active (Thermal Design)
4/ 7/ 8/
I
CC
Stop Grant
9/
I
CC
Stop Clock
10/
CLK Capacitance
Input Capacitance
Output or I/O Capacitance
I
LO
I
CCU
I
IH
I
IL
V
IL
V
IH
V
OL
V
OH
-15
15
-0.3
2.0
Address, Data, BEn = 4.0mA
Definition, Control = 5.0mA
I
OH
= -2.0 mA
f
OP
= 100 MHz
f
OP
= 75 MHz
f
OP
= 100 MHz
f
OP
= 75 MHz
f
OP
= 100 MHz
f
OP
= 75 MHz
f
OP
= 0 MHz
@ 1 MHz 4/
@ 1 MHz 4/
@ 1 MHz 4/
+15
35
50
200
-400
0.8
V
CC5
+ 0.3
0.45
2.4
1075
825
50
20
600
C
CLK
C
IN
C
OUT
Notes:
1.
This parameter is for inputs with pull-downs and VIH = 2.4V.
2.
This parameter is for inputs with pull-ups and VIL = 0.4V.
3.
When the processor is in Stop Grant state, the ICCU of the host processor is less than 2 mA.
4.
Not 100% tested.
5.
This parameter is for inputs with pull-downs and VIH = 2.4V. (SRESET pin only).
6.
This parameter is for proper power supply selection. It is measured using the worst case instruction mix at VCC = 3.6V.
7.
The maximum current column is for thermal design power dissipation. It is measured using the worst case instruction mix at VCC =
3.3V.
8.
The typical current column is the typical operating current in a system. This value is measured in a system using a typical device at
VCC = 3.3V, running Microsoft Windows 3.1 at an idle condition. This typical value is dependent upon the specific system
configuration.
9.
The ICC Stop Grant specification refers to the ICC value once the processor enters the Stop Grant or Auto HALT Power Down state.
10.
The ICC Stop Clock specification refers to the ICC value once the processor enters the Stop Clock state. The VIH and VIL levels
must be equal to VCC and 0V, respectively, in order to meet the ICC Stop Clock specifications.
0507.98Rev0
Specification and design are subject to change without notice.
2
--4.3--
©1998 Space Electronics Inc.
All rights reserved
80486DX4RP
R
ADIATION
H
ARDENED
PARAMETER
CLK Frequency
80486DX4RP-25
80486DX4RP-33
CLK Period
80486DX4RP-25
80486DX4RP-33
CLK Period Stability
80486DX4RP-25
80486DX4RP-33
CLK High Time
80486DX4RP-25
80486DX4RP-33
CLK Low Time
80486DX4RP-25
80486DX4RP-33
CLK Fall Time
80486DX4RP-25
80486DX4RP-33
CLK Rise Time
80486DX4RP-25
80486DX4RP-33
A2 - A31, PWT, PCD,
BE0-3#, M/IO#, D/C#, W/R#,
ADS#, LOCK#, BREQ, HLDA,
SMIACT#, FERR# Valid Delay
80486DX4RP-25
80486DX4RP-33
A2 - A31, PWT, PCD,
BE0-3#, M/IO#, D/C#, W/R#,
ADS#, LOCK#, BREQ, HLDA,
Float Delay
80486DX4RP-25
80486DX4RP-33
PCHK# Valid Delay
80486DX4RP-25
80486DX4RP-33
BLAST#, PLOCK# SMIACT #
Valid Delay
80486DX4RP-25
80486DX4RP-33
BLAST#, PLOCK#
Float Delay
80486DX4RP-25
80486DX4RP-33
D0-D31, DP0-DP3 Write Data
Valid Delay
80486DX4RP-25
80486DX4RP-33
32-B
IT
M
ICROPROCESSOR
SYMBOL
MIN
8
8
t
1
40
30
125
125
+250
ns
ns
ps
MAX
25
33
UNIT
MHz
80486DX4RP AC ELECTRICAL CHARACTERISTICS
(V
CC
=3.3V
±
0.3V, T
A
= 0
°
C to +85
°
C, C
L
= 50pF, unless otherwise specified)
TEST CONDITION
1/
2/, 5/
t
1a
at 2V
t
2
14
11
ns
at 0.8V
t
3
4
11
ns
2V to 0.8V
t
4
4
3
ns
0.8V to 2V
t
5
4
3
t
6
ns
3
3
2/,
t
7
19
14
ns
28
20
t
8
3
3
t
8a
3
3
2/
t
9
28
20
t
10
3
3
20
14
24
14
24
14
ns
ns
ns
ns
ns
Notes:
1.
0-MHz operation is guarantee when the STPCLK# and Stop Grant bus cycle protocol is used.
2.
Not 100% tested, guaranteed by design characterization.
3.
All timing specifications assume CL = 50pF. A reset pulse width of 15 CLK cycles is required for warm resets (RESET or SRESET).
Power-up resets (cold resets) require RESET to be asserted for at least 1ms after VCC and CLK are stable.
4.
For adjacent clocks, assumes frequency of operation is constant.
5.
STPCLK# input should be used to change frequency of operation.
0507.98Rev0
Specification and design are subject to change without notice.
3
--4.3--
©1998 Space Electronics Inc.
All rights reserved
80486DX4RP
R
ADIATION
H
ARDENED
32-B
IT
M
ICROPROCESSOR
TEST CONDITION
2/
SYMBOL
t
11
28
20
t
12
8
5
t
13
3
3
t
14
8
5
t
15
3
3
t
16
8
5
t
17
3
3
t
18
8
6
t
18a
8
7
t
19
3
3
4/
t
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
MAX
UNIT
80486DX4RP AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
=3.3V
±
0.3V, T
A
= 0
°
C to +85
°
C, C
L
= 50pF, unless otherwise specified)
PARAMETER
D0-D31, DP0-DP31 Write Data
Float Delay
1/
80486DX4RP-25
80486DX4RP-33
EADS#, INV Setup Time
80486DX4RP-25
80486DX4RP-33
EADS#, INV Hold Time
80486DX4RP-25
80486DX4RP-33
KEN#, BS16#, BS#, Setup Time
80486DX4RP-25
80486DX4RP-33
KEN#, BS16#, BS# Hold Time
80486DX4RP-25
80486DX4RP-33
RDY#, BRDY# Setup Time
80486DX4RP-25
80486DX4RP-33
RDY#, BRDY# Hold Time
80486DX4RP-25
80486DX4RP-33
HOLD, AHOLD Setup Time
80486DX4RP-25
80486DX4RP-33
BOFF# Setup Time
80486DX4RP-25
80486DX4RP-33
HOLD, AHOLD, BOFF# Hold
Time
80486DX4RP-25
80486DX4RP-33
FLUSH#, A20M#, NMI, INTR,
SMI#, STPCLK#, SRESET,
RESET, IGNNE# Setup Time
80486DX4RP-25
80486DX4RP-33
FLUSH#, A20M#, NMI, INTR,
SMI#, STPCLK#, SRESET,
RESET, IGNNE# Hold Time
80486DX4RP-25
80486DX4RP-33
D0-D31, DP0-DP3, A4-A31
Read Setup Time
80486DX4RP-25
80486DX4RP-33
D0-D31, DP0-DP3, A4-A31
Read Hold Time
80486DX4RP-25
80486DX4RP-33
8
5
4/
t
21
ns
3
3
t
22
5
5
t
23
3
3
ns
ns
ns
Notes:
1.
0-MHz operation is guarantee when the STPCLK# and Stop Grant bus cycle protocol is used.
2.
Not 100% tested, guaranteed by design characterization.
3.
All timing specifications assume CL = 50pF. A reset pulse width of 15 CLK cycles is required for warm resets (RESET or SRESET).
Power-up resets (cold resets) require RESET to be asserted for at least 1ms after VCC and CLK are stable.
4.
For adjacent clocks, assumes frequency of operation is constant.
5.
STPCLK# input should be used to change frequency of operation.
0507.98Rev0
Specification and design are subject to change without notice.
4
--4.3--
©1998 Space Electronics Inc.
All rights reserved
80486DX4RP
R
ADIATION
H
ARDENED
32-B
IT
M
ICROPROCESSOR
TEST CONDITION
SYMBOL
MIN
MAX
UNIT
80486DX4RP AC SPECIFICATIONS FOR THE TEST ACCESS PORT
(V
CC
=3.3V
±
0.3V, T
A
= 0
°
C to +85
°
C, C
L
= 50pF, unless otherwise specified)
PARAMETER
TCK Frequency
1/
t
24
25
MHz
TCK Period
t
25
40
ns
TCK High Time
at 2.0V
t
26
10
ns
TCK Low Time
at 0.8V
t
27
10
ns
TCK Rise Time
2/
t
28
4
ns
TCK Fall Time
2/
t
29
4
ns
TDI, TMS Setup Time
3/
t
30
8
ns
TDI, TMS Hold Time
3/
t
31
7
ns
TDO Valid Delay
3/
t
32
3
25
ns
TDO Float Delay
3/
t
33
30
ns
All Outputs (Non-Test) Valid Delay
3/
t
34
3
25
ns
All Outputs (Non-Test) Float Delay
3/
t
35
36
ns
All Inputs (Non-Test) Setup Time
3/
t
36
8
ns
All Inputs (Non-Test) Hold Setup 3/
t
37
7
ns
Notes:
1. TCK period < CLK period.
2. Rise/Fall times are measured between 0.8V and 2.0V. Rise/Fall times can be relaxed by 1 ns per 10-ns increase
in TCK period.
3. Parameters t
30
- t
37
are measured from TCK.
0507.98Rev0
Specification and design are subject to change without notice.
5
--4.3--
©1998 Space Electronics Inc.
All rights reserved
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
