FINAL
COM’L: -12/15/20, Q-20/25
MACH435-12/15/20, Q-20/25
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
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84 Pins in PLCC
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128 Macrocells
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12 ns tPD
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83.3 MHz fCNT
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70 Inputs with pull-up resistors
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64 Outputs
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192 Flip-flops
— 128 Macrocell flip-flops
— 64 Input flip-flops
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Up to 20 product terms per function, with XOR
Lattice Semiconductor
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Flexible clocking
— Four global clock pins with selectable edges
— Asynchronous mode available for each
macrocell
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8 “PAL33V16” blocks
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Input and output switch matrices for high
routability
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Fixed, predictable, deterministic delays
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Pin compatible with MACH130, MACH131,
MACH230, and MACH231
GENERAL DESCRIPTION
The MACH435 is a member of our high-performance
EE CMOS MACH 4 family. This device has approxi-
mately twelve times the macrocell capability of the
popular PAL22V10, with significant density and func-
tional features that the PAL22V10 does not provide.
The MACH435 consists of eight PAL blocks intercon-
nected by a programmable central switch matrix. The
central switch matrix connects the PAL blocks to each
other and to all input pins, providing a high degree of
connectivity between the fully-connected PAL blocks.
This allows designs to be placed and routed efficiently.
Routability is further enhanced by an input switch matrix
and an output switch matrix. The input switch matrix
provides input signals with alternative paths into the
central switch matrix; the output switch matrix provides
flexibility in assigning macrocells to I/O pins.
The MACH435 has macrocells that can be configured
as synchronous or asynchronous. This allows designers
to implement both synchronous and asynchronous logic
together on the same device. The two types of design
can be mixed in any proportion, since the selection on
each macrocell affects only that macrocell.
Up to 20 product terms per function can be assigned. It
is possible to allocate some product terms away from a
macrocell without losing the use of that macrocell for
logic generation.
The MACH435 macrocell provides either registered or
combinatorial outputs with programmable polarity. If a
registered configuration is chosen, the register can be
configured as D-type, T-type, J-K, or S-R to help reduce
the number of product terms used. The flip-flop can also
be configured as a latch. The register type decision can
be made by the designer or by the software.
All macrocells can be connected to an I/O cell through
the output switch matrix. The output switch matrix
makes it possible to make significant design changes
while minimizing the risk of pinout changes.
Publication#
17469
Rev.
E
Issue Date:
May 1995
Amendment
/0
FUNCTIONAL DESCRIPTION
The MACH435 consists of eight PAL blocks connected
by a central switch matrix. There are 64 I/O pins and 6
dedicated input pins feeding the central switch matrix.
These signals are distributed to the eight PAL blocks for
efficient design implementation. There are 4 global
clock pins that can also be used as dedicated inputs.
All inputs and I/O pins have built-in pull-up resistors.
While it is always good design practice to tie unused
pins high, the pull-up resistors provide design security
and stability in the event that unused pins are left
disconnected.
The Product-Term Array
The MACH435 product-term array consists of 80
product terms for logic use, eight product terms for
output enable use, and two product terms for global PAL
block initialization. Each macrocell has a nominal
allocation of 5 product terms for logic, although the logic
allocator allows for logic redistribution. Each I/O pin has
its own individual output enable term. The initialization
product terms provide asynchronous reset or preset to
synchronous-mode macrocells in the PAL block.
The Logic Allocator
The logic allocator in the MACH435 takes the 80 logic
product terms and allocates them to the 16 macrocells
as needed. Each macrocell can be driven by up to 20
product terms if in synchronous mode, or 18 product
terms if in asynchronous mode. When product terms are
routed away from a macrocell, it is possible to route all 5
product terms away, which precludes the use of the
macrocell for logic generation; or it is possible to route
only 4 product terms away, leaving one for simple
function generation. The design software automatically
configures the logic allocator when fitting the design into
the device.
The logic allocator also provides an exclusive-OR gate.
This gate allows generation of combinatorial exclusive-
OR logic, such as comparison or addition. It allows
registered exclusive-OR functions, such as CRC gen-
eration, to be implemented more efficiently. It also
makes in possible to emulate all flip-flop types with a
D-type flip-flop. Register type emulation is automatically
handled by the design software.
Table 1 illustrates which product term clusters are
available to each macrocell within a PAL block. Refer to
Figure 1 for cluster and macrocell numbers.
The PAL Blocks
Each PAL block in the MACH435 (Figure 1) contains a
clock generator, a 90-product-term logic array, a logic
allocator, 16 macrocells, an output switch matrix, 8 I/O
cells, and an input switch matrix. The central switch
matrix feeds each PAL block with 33 inputs. This makes
the PAL block look effectively like an independent
“PAL33V16” with 8 to 16 buried macrocells.
In addition to the logic product terms, individual output
enable product terms and two PAL block initialization
product term are provided. Each I/O pin can be
individually enabled. All flip-flops that are in the
synchronous mode within a PAL block are initialized
together by either of the PAL block initialization product
terms.
The Central Switch Matrix and Input
Switch Matrix
The MACH435 central switch matrix is fed by the input
switch matrices in each PAL block. Each PAL block
provides 16 internal feedback signals, 8 registered input
signals, and 8 I/O pin signals to the input switch matrix.
Of these 32 signals, 24 decoded signals are provided to
the central switch matrix by the input switch matrix. The
central switch matrix distributes these signals back to
the PAL blocks in a very efficient manner that provides
for high performance. The design software automati-
cally configures the input and central switch matrices
when fitting a design into the device.
The Clock Generator
Each PAL block has a clock generator that can generate
four clock signals for use throughout the PAL block.
These four signals are available to all macrocells and
I/O cells in the PAL block, whether in synchronous or
asynchronous mode. The clock generator chooses the
four signals from the eight possible signals given by the
true and complement versions of the four global clock
pin signals.
MACH435-12/15/20, Q-20/25
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