Data Sheet
FEATURES
Low V
OS
(V
BE
match): 40 µV typical, 100 µV maximum
Low TCV
OS
: 0.5 µV/°C maximum
High h
FE
: 500 minimum
Excellent h
FE
linearity from 10 nA to 10 mA
Low noise voltage: 0.23 µV p-p from 0.1 Hz to 10 Hz
High breakdown: 45 V min
Matched Monolithic
Dual Transistor
MAT01
PIN CONNECTION DIAGRAM
MAT01
TOP VIEW
(Not to Scale)
C
1
C
2
1
6
B
1 2
E
1 3
5
B
2
APPLICATIONS
Weigh scales
Low noise, op amp, front end
Current mirror and current sink/source
Low noise instrumentation amplifiers
Voltage controlled attenuators
Log amplifiers
4
E
2
00282-001
NOTES
1. SUBSTRATE IS CONNECTED TO CASE.
Figure 1.
GENERAL DESCRIPTION
The
MAT01
is a monolithic dual NPN transistor. An exclusive
silicon nitride triple passivation process provides excellent
stability of critical parameters over both temperature and time.
Matching characteristics include offset voltage of 40 µV,
temperature drift of 0.15 µV/°C, and h
FE
matching of 0.7%.
High h
FE
is provided over a six decade range of collector
current, including an exceptional h
FE
of 590 at a collector
current of only 10 nA. The high gain at low collector current
makes the
MAT01
ideal for use in low power, low level input
stages.
Rev. D
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MAT01
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Connection Diagram ................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 5
Data Sheet
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Test Circuits........................................................................................8
Applications Information .................................................................9
Typical Applications ....................................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
9/14—Rev. C to Rev. D
Changes to Figure 4 and Figure 7 ................................................... 6
4/13—Rev. B to Rev. C
Updated Format .................................................................. Universal
Added Applications Section, Deleted Figure 2,
Renumbered Sequentially................................................................ 1
Deleted Table 3, Renumbered Sequentially................................... 4
Changes to Table 3 ............................................................................ 5
Changes to Typical Performance Characteristics Section ........... 6
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
2/02—Rev. A to Rev. B
Edits to Features.................................................................................1
Deleted Wafer Test Limits ................................................................3
Deleted DICE Characteristics ..........................................................3
Edits to Table 5 ...................................................................................7
Rev. D | Page 2 of 12
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
CB
= 15 V, I
C
= 10 µA, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
VOLTAGE
Breakdown Voltage
Offset Voltage
Offset Voltage Stability
First Month
1
Long Term
2
CURRENT
Offset Current
Bias Current
Current Gain
Symbol
BV
CEO
V
OS
V
OS
/Time
Test Conditions/Comments
I
C
= 100 µA
MAT01AH
Min Typ Max
45
0.04
2.0
0.2
0.1
13
590
770
840
0.7
0.8
0.23
0.60
7.0
6.1
6.0
0.5
2
15
50
20
0.12
0.8
450
2.8
8.5
0.6
20
250
3.0
0.1
MAT01GH
Min Typ Min
45
0.10
2.0
0.2
0.2
18
430
560
610
1.0
1.2
0.23
0.60
7.0
6.1
6.0
0.8
3
25
90
30
0.12
0.8
450
2.8
8.5
3.2
40
0.5
MAT01
Unit
V
mV
µV/Mo
µV/Mo
nA
nA
I
OS
I
B
h
FE
Current Gain Match
NOISE
Low Frequency Noise Voltage
Broadband Noise Voltage
Noise Voltage Density
∆h
FE
I
C
= 10 nA
I
C
= 10 µA
I
C
= 10 mA
I
C
= 10 µA
100 nA ≤ I
C
≤ 10 mA
0.1 Hz to 10 Hz
3
1 Hz to 10 kHz
f
O
= 10 Hz
3
f
O
= 100 Hz
3
f
O
= 1000 Hz
3
0 ≤ V
CB
≤ 30 V
0 ≤ V
CB
≤ 30 V
V
CB
= 30 V, I
E
= 0
4
V
CE
= 30 V, V
BE
= 0
4, 5
V
CC
= 30 V
5
I
B
= 0.1 mA, I
C
= 1 mA
I
B
= 1 mA, I
C
= 10 mA
V
CE
= 10 V, I
C
= 10 mA
V
CB
= 15 V, I
E
= 0
V
CC
= 0
500
8.0
%
%
µV p-p
µV rms
nV/√Hz
nV/√Hz
nV/√Hz
µV/V
pA/V
pA
pA
pA
V
V
MHz
pF
pF
e
n
p-p
e
n
rms
e
n
0.4
9.0
7.6
7.5
3.0
15
50
200
200
0.20
0.4
9.0
7.6
7.5
8.0
70
200
400
400
0.25
OFFSET VOLTAGE/CURRENT
Offset Voltage Change
Offset Current Change
LEAKAGE
Collector to Base Leakage Current
Collector to Emitter Leakage Current
Collector to Collector Leakage Current
SATURATION
Collector Saturation Voltage
GAIN BANDWIDTH PRODUCT
CAPACITANCE
Output Capacitance
Collector to Collector Capacitance
1
2
∆V
OS
/∆V
CB
∆I
OS
/∆V
CB
I
CBO
I
CES
I
CC
V
CE(SAT)
f
T
C
OB
C
CC
Exclude first hour of operation to allow for stabilization.
Parameter describes long-term average drift after first month of operation.
3
Sample tested.
4
The collector to base (I
CBO
) and collector to emitter (I
CES
) leakage currents can be reduced by a factor of 2 to 10 times by connecting the substrate (package) to a
potential that is lower than either collector voltage.
5
I
CC
and I
CES
are guaranteed by measurement of I
CBO
.
Rev. D | Page 3 of 12
MAT01
V
CB
= 15 V, I
C
= 10 µA, −55°C ≤ T
A
≤ +125°C, unless otherwise noted.
Table 2.
Parameter
OFFSET VOLTAGE/CURRENT
Offset Voltage
Average Offset Voltage Drift
1
Offset Current
Average Offset Current Drift
2
BIAS CURRENT
CURRENT GAIN
LEAKAGE CURRENT
Collector to Base Leakage Current
Collector to Emitter Leakage Current
Collector to Collector Leakage Current
1
Data Sheet
Symbol
V
OS
TCV
OS
I
OS
TCI
OS
Ι
Β
h
FE
I
CBO
I
CES
I
CC
Test Conditions/Comments
MAT01AH
Min Typ Max
0.06
0.15
0.9
10
28
400
15
50
30
0.15
0.50
8.0
90
60
MAT01GH
Min Typ Min
0.14
0.35
1.5
15
36
300
25
90
50
0.70
1.8
15.0
150
130
Unit
mV
µV/°C
nA
pA/°C
nA
167
T
A
= 125°C, V
CB
= 30 V, I
E
= 0
3
T
A
= 125°C, V
CE
= 30 V, V
BE
= 0
1, 3
T
A
= 125°C, V
CC
= 30 V
1
77
80
300
200
200
400
400
nA
nA
nA
V
Guaranteed by V
OS
test
TCVOS
≅
OS
for
VOS
<<
VBE
,
T
= 298 K for T
A
= 25°C.
T
2
Guaranteed by I
OS
test limits over temperature.
3
The collector to base (I
CBO
) and collector to emitter (I
CES
) leakage currents can be reduced by a factor of 2 to 10 times by connecting the substrate (package) to a
potential that is lower than either collector voltage.
(
)
Rev. D | Page 4 of 12
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
1
Breakdown Voltage of
Collector to Base Voltage (BV
CBO
)
Collector to Emitter Voltage (BV
CEO
)
Collector to Collector Voltage (BV
CC
)
Emitter to Emitter Voltage (BV
EE
)
Emitter to Base Voltage (BV
EBO
)
2
Current
Collector (I
C
)
Emitter (I
E
)
Total Power Dissipation
Case Temperature ≤ 40°C
3
Ambient Temperature ≤ 70°C
4
Temperature Range
Operating
Junction
Storage
Lead Temperature (Soldering, 60 sec)
1
2
MAT01
Rating
45 V
45 V
45 V
45 V
5V
25 mA
25 mA
1.8 W
500 mW
−55°C to +125°C
−55°C to +150°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Absolute maximum ratings apply to packaged devices.
Application of reverse bias voltages in excess of rating shown can result in
degradation of h
FE
and h
FE
matching characteristics. Do not attempt to
measure BV
EBO
greater than the 5 V rating.
3
Rating applies to applications using heat sinking to control case
temperature. Derate linearity at 16.4 mW/°C for case temperatures above
40°C.
4
Rating applies to applications not using heat sinking; device in free air only.
Derate linearity at 6.3 mW/°C for ambient temperatures above 70°C.
Rev. D | Page 5 of 12
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