Available at 80-200MHz, with mode bit dependent output
clock frequencies
x
64GB physical address space
x
Processor family for a wide variety of embedded
applications
– LAN switches
– Routers
– Color printers
x
Description
The IDT79R4700 64-bit RISC Microprocessor is both software and
pin-compatible with the R4
XXX
processor family. With 64-bit processing
capabilities, the R4700 provides more computational power and data
movement bandwidth than is delivered to typical embedded systems by
32-bit processors.
The R4700 is upwardly software compatible with the IDT79R3000
™
microprocessor family, including the IDTRISController
™
79R3051
™
,
R3052
™
, R3041
™
, R3081
™
as well as the R4640
™
, R4650
™
, RC64474/
475
™
and R5000
™
. An array of development tools facilitates rapid
development of R4700-based systems, allowing a variety of customers
access to the MIPS Open Architecture philosophy.
Block Diagram
Data Tag A
Data Set A
Store Buffer
SysAD
Instruction Select
Write Buffer
Read Buffer
Data Set B
DBus
IBus
Control
Tag
Floating-point
Register File
Unpacker/Packer
Floating-point Control
DTLB Physical
Data Tag B
Instruction Set A
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Instruction Register
Instruction Set B
AuxTag
Load Aligner
Integer Control
Joint TLB
Integer Register File
Integer/Address Adder
Data TLB Virtual
Floating-point
Add/Sub/Cvt/Div/Sqrt
Integer Divide
Coprocessor 0
DVA
Shifter/Store Aligner
Logic Unit
PC Incrementer
Floating-point/Integer
Multiply
Phase Lock Loop, Clocks
System/Memory
Control
IVA
Branch Adder
Instruction TLB Virtual
Program Counter
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.
1 of 25
2001 Integrated Device Technology, Inc.
April 10, 2001
DSC 9096
IDT79R4700
This data sheet provides an overview of the R4700’s CPU features
and architecture. A more detailed description of this processor is
provided in the
IDT79R4700 RISC Processor Hardware User’s Manual,
available from Integrated Device Technology (IDT). Information on
development support, applications notes and complementary products
is available on the IDT Web site
www.idt.com
or through your local IDT
sales representative.
Note:
Throughout this data sheet and any other IDT materials for this
device, the R4700 indicates a 5V part; RV4700 designates a reduced
voltage (3V) part; and the RC4700 reflects either.
resource dependencies are made transparent to the programmer,
insuring transportability among implementations of the MIPS instruction
set architecture.
The MIPS integer unit implements a load/store architecture with
single cycle ALU operations (logical, shift, add, sub) and an autono-
mous multiply/divide unit. Register resources include:
x
32 general-purpose orthogonal integer registers
x
HI/LO result registers, for the integer multiply/divide unit
x
Program counter
Also, the on-chip floating-point co-processor adds 32 floating-point
registers and a floating-point control/status register.
Register File
The R4700 has 32 general-purpose registers (shown in Figure 2).
These registers are used for scalar integer operations and address
calculation. The register file consists of two read ports and one write
port and is fully bypassed to minimize operation latency in the pipeline.
General Purpose Registers
63
0
0
r1
r2
•
•
•
•
r29
r30
r31
Multiply/Divide Registers
63
HI
63
LO
Program Counter
0
PC
0
0
PageMask
5*
EntryH i
10*
47
EntryLo0
2*
EntryLo1
3*
3*
C ount
9*
Status
12*
EPC
14*
Index
0*
C ontext
4*
BadVAddr
8*
PRId
15*
TagH i
29*
EC C
26*
Com pare
11*
Cause
13*
ErrorEPC
30*
XC ontext
20*
LLAddr
17*
Config
16*
TagLo
28*
CacheErr
27*
TLB
Random
1*
Wired
6*
0
(entries protected
from TLBW R )
* Register number
63
Figure 1 The RC4700 CPO Registers
Hardware Overview
The RC4700 processor family brings a high-level of integration
designed for high-performance computing. The R4700’s key elements
are briefly described below. A more detailed explanation of each
subsystem is available in the user’s manual.
Pipeline
The RC4700 uses a simple 5-stage pipeline, similar to the pipeline
structure implemented in the IDT79R32364. This pipeline’s simplicity
allows the RC4700 to be lower cost and lower power than super-scalar
or super-pipelined processors. The pipeline stages are shown in Figure
3 on page 3.
Integer Execution Engine
The R4700 implements the MIPS-III Instruction Set architecture and
is upwardly compatible with applications that run on earlier generation
parts.
Implementation of the MIPS-III architecture results in 64-bit opera-
单片机
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