19-1236; Rev 0; 6/97
KIT
ATION
EVALU
BLE
AVAILA
Low-Power, 90Msps, Dual 6-Bit ADC
____________________________Features
o
Two Matched 6-Bit ADCs
o
High Sampling Rate: 90Msps per ADC
o
Low Power Dissipation: 350mW
o
Excellent Dynamic Performance:
5.85 ENOB with 20MHz Analog Input
5.7 ENOB with 50MHz Analog Input
o
±1/4LSB INL and DNL (typ)
o
Internal Bandgap Voltage Reference
o
Internal Oscillator with Overdrive Capability
o
55MHz (-0.5dB) Bandwidth Input Amplifiers with
True Differential Inputs
o
User-Selectable Input Full-Scale Range
(125mVp-p, 250mVp-p, or 500mVp-p)
o
1/4LSB Channel-to-Channel Offset Matching (typ)
o
0.1dB Gain and 0.5° Phase Matching (typ)
o
Single-Ended or Differential Input Drive
o
Flexible, 3.3V, CMOS-Compatible Digital Outputs
_______________General Description
The MAX1003 is a dual, 6-bit analog-to-digital converter
(ADC) that combines high-speed, low-power operation
with a user-selectable input range, an internal refer-
ence, and a clock oscillator. The dual parallel ADCs are
designed to convert in-phase (I) and quadrature (Q)
analog signals into two 6-bit, offset-binary-coded digital
outputs at sampling rates up to 90Msps. The ability to
directly interface with baseband I and Q signals makes
the MAX1003 ideal for use in direct-broadcast satellite,
VSAT, and QAM16 demodulation applications.
The MAX1003 input amplifiers feature true differential
inputs, a -0.5dB analog bandwidth of 55MHz, and user-
programmable input full-scale ranges of 125mVp-p,
250mVp-p, or 500mVp-p. With an AC-coupled input
signal, matching performance between input channels
is typically better than 0.1dB gain, 1/4LSB offset, and
0.5° phase. Dynamic performance is 5.85 effective
number of bits (ENOB) with a 20MHz analog input sig-
nal, or 5.7 ENOB with a 50MHz signal.
The MAX1003 operates with +5V analog and +3.3V digi-
tal supplies for easy interfacing to +3.3V-logic-compati-
ble digital signal processors and microprocessors. It
comes in a 36-pin SSOP package.
MAX1003
________________________Applications
Direct Broadcast Satellite (DBS) Receivers
VSAT Receivers
Wide Local Area Networks (WLANs)
Cable Television Set-Top Boxes
______________Ordering Information
PART
MAX1003CAX
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
36 SSOP
Pin Configuration appears at end of data sheet.
_________________________________________________________Functional Diagram
IOCC+
IIN+
INPUT
AMP
I
OFFSET
CORREC-
TION I
IOCC-
6
6
IIN-
ADC
I
VREF
DATA
BUFFER
I
DI0–DI5
CLOCK
OUT
BANDGAP
REFERENCE
CLOCK
DRIVER
DCLK
TNK+
TNK-
GAIN
OFFSET
CORREC-
TION Q
QIN+
INPUT
AMP
Q
QOCC+
MAX1003
VREF
ADC
Q
6
DATA
BUFFER
Q
6
DQ0–DQ5
QIN-
QOCC-
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Low-Power, 90Msps, Dual 6-Bit ADC
MAX1003
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND ............................................................-0.3V to 6.5V
V
CCO
to OGND ........................................................-0.3V to 6.5V
GND to OGND ........................................................-0.3V to 0.3V
Digital and Clock Output Pins to OGND...-0.3V to V
CCO
(10sec)
All Other Pins to GND...............................................-0.3V to V
CC
Continuous Power Dissipation (T
A
= +70°C)
SSOP (derate 11.8mW/°C above +70°C) ...................941mW
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +5V ±5%, V
CCO
= 3.3V ±300mV, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
DC ACCURACY
(Note 1)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Full-Scale Input Range
RES
INL
DNL
V
FSH
V
FSM
V
FSL
Input Open-Circuit Voltage
Input Resistance
Input Capacitance
Common-Mode Voltage Range
OSCILLATOR INPUTS
Oscillator Input Resistance
Digital Outputs Logic-High
Voltage
Digital Outputs Logic-Low
Voltage
POWER SUPPLY
Supply Current
Power-Supply Rejection Ratio
Digital Outputs Supply Current
Power Dissipation
I
CC
PSRR
I
CCO
PD
V
CC
= 4.75V to 5.25V (Note 3)
20MHz, full-scale I and Q analog inputs,
C
L
= 15pF (Note 4)
350
63
-75
104
-40
21
mA
dB
mA
mW
R
OSC
Other oscillator input tied to V
CC
+ 0.3V
4.8
8
12.1
kΩ
DIGITAL OUTPUTS (DI0–DI5, DQ0–DQ5)
V
OH
V
OL
I
SOURCE
= 50µA
I
SINK
= 400µA
0.7V
CCO
0.5
V
V
V
AOC
R
IN
C
IN
V
CM
Guaranteed by design
Other analog input driven with external source
(Note 2)
1.75
No missing codes over temperature
GAIN = V
CC
(high gain)
GAIN = open (mid gain)
GAIN = GND (low gain)
6
-0.5
-0.5
118.75
237.5
475
2.25
13
±0.25
±0.25
125
250
500
2.35
20
3
0.5
0.5
131.25
262.5
525
2.45
29
5
2.75
V
kΩ
pF
V
mVp-p
Bits
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INVERTING AND NONINVERTING ANALOG INPUTS
2
_______________________________________________________________________________________
Low-Power, 90Msps, Dual 6-Bit ADC
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +5V ±5%, V
CCO
= 3.3V ±300mV, T
A
= +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1003
DYNAMIC PERFORMANCE
(Gain = open, external 90MHz clock (Figure 7), V
INI
= V
INQ
= 20MHz sine, amplitude -1dB below
full scale, unless otherwise noted.)
Maximum Sample Rate
Analog Input -0.5dB Bandwidth
f
MAX
BW
ENOB
M
Effective Number of Bits
ENOB
H
ENOB
L
Signal-to-Noise plus Distortion
Ratio
Input Offset (Note 5)
Crosstalk Between ADCs
Offset Mismatch Between ADCs
Amplitude Match Between
ADCs
Phase Match Between ADCs
Clock to Data Propagation
Delay
Data Valid Skew
Input to DCLK Delay
Aperture Delay
Pipeline Delay
SINAD
OFF
XTLK
OMM
AM
PM
(Note 5)
-0.5
-0.2
-2
GAIN = GND, open, V
CC
GAIN = open (mid gain)
GAIN = open (mid gain), f
IN
= 50MHz,
-1dB below full scale
GAIN = V
CC
(high gain)
GAIN = GND (low gain)
GAIN = open (mid gain)
I channel
Q channel
35.5
-0.5
-0.5
-55
±0.25
±0.1
±0.5
0.5
0.2
2
5.6
90
55
5.85
5.7
5.8
5.85
37
0.5
0.5
dB
LSB
dB
LSB
dB
degrees
Bits
Msps
MHz
TIMING CHARACTERISTICS
(Data outputs: R
L
= 1MΩ, C
L
= 15pF)
t
PD
t
SKEW
t
DCLK
t
AD
PD
(Note 6)
(Note 6)
TNK+ to DCLK (Note 6)
Figure 8
Figure 8
3.6
1.5
5.3
7.5
1
ns
ns
ns
ns
clock
cycle
Note 1:
Best-fit straight-line linearity method.
Note 2:
A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4 and 5).
Note 3:
PSRR is defined as the change in the mid-gain full-scale range as a function of the variation in V
CC
supply voltage,
expressed in decibels.
Note 4:
The current in the V
CCO
supply is a strong function of the capacitive loading on the digital outputs. To minimize supply tran-
sients and achieve optimal dynamic performance, reduce the capacitive-loading effects by keeping line lengths on the dig-
ital outputs to a minimum.
Note 5:
Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2 and 3).
Note 6:
t
PD
and t
SKEW
are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. t
DCLK
is measured from the 50% level of the clock-overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-
itive load on the outputs is 15pF.
_______________________________________________________________________________________
3
Low-Power, 90Msps, Dual 6-Bit ADC
MAX1003
__________________________________________Typical Operating Characteristics
(V
CC
= +5V ±5%, V
CCO
= 3.3V ±300mV, f
CLK
= 90Msps, GAIN = open (midgain) MAX1003 evaluation kit, T
A
= +25°C, unless
otherwise noted.)
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
MAX1003-01
ANALOG INPUT BANDWIDTH
0
-0.2
MAGNITUDE (dB)
MAX1003-02
EFFECTIVE NUMBER OF BITS
vs. SAMPLING/CLOCK FREQUENCY
MAX1003-03
6.0
6.0
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBER OF BITS
5.8
5.9
5.6
5.8
-0.4
-0.6
-0.8
5.4
5.7
5.2
f
CLK
= 90Msps
5.0
10
ANALOG INPUT FREQUENCY (MHz)
100
5.6
f
IN
= 20MHz
-1.0
1
10
ANALOG INPUT FREQUENCY (MHz)
100
5.5
1
10
CLOCK FREQUENCY (MHz)
100
OSCILLATOR OPEN-LOOP PHASE NOISE
vs. FREQUENCY OFFSET
MAX1003-04
FFT PLOT
f
IN
= 19.9512MHz
f
CLK
= 90.000MHz
1024 POINTS
AC COUPLED
SINGLE ENDED
AVERAGED
MAX1003-05
-50
0
-70
PHASE NOISE (dBc)
AMPLITUDE (dB)
1k
10k
100k
1M
-20
-90
-110
-40
-130
-60
0
9
18
27
36
45
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY (MHz)
INTEGRAL NONLINEARITY
vs. CODE
MAX1003-06
DIFFERENTIAL NONLINEARITY
vs. CODE
MAX1003-07
0.50
0.50
0.25
DNL (LSB)
INL (LSB)
0.25
0
0
-0.25
-0.25
-0.50
0
10
20
30
CODE
40
50
60 64
-0.50
0
10
20
30
CODE
40
50
60 64
4
_______________________________________________________________________________________
Low-Power, 90Msps, Dual 6-Bit ADC
______________________________________________________________Pin Description
PIN
1
2
3
4
5
6
7, 11, 12,
18, 19
8
9
10
13
14
15
16
17
20–25
26, 28
27
29
30–35
36
NAME
GAIN
IOCC+
IOCC-
IIN+
IIN-
V
CC
GND
V
CC
TNK+
TNK-
V
CC
QIN-
QIN+
QOCC-
QOCC+
DQ5–DQ0
V
CCO
OGND
DCLK
DI0–DI5
V
CC
FUNCTION
Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1).
Positive I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
Negative I-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
I-Channel Noninverting Analog Input
I-Channel Inverting Analog Input
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 7).
Analog Ground
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 11).
Positive Oscillator/Clock Input
Negative Oscillator/Clock Input
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 12).
Q-Channel Inverting Analog Input
Q-Channel Noninverting Analog Input
Negative Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
Positive Q-Channel Offset-Correction Compensation. Connect a 0.22µF capacitor for AC-coupled
inputs. Ground for DC-coupled inputs.
Q-Channel Digital Outputs 0–5. DQ5 is the most significant bit (MSB).
Digital Output Supply, +3.3V ±300mV. Bypass each with a 47pF capacitor to OGND (pin 27).
Digital Output Ground
Digital Clock Output. Frames the output data.
I-Channel Digital Outputs 0–5. DI5 is the most significant bit (MSB).
+5V ±5% Supply. Bypass with a 0.01µF capacitor to GND (pin 19).
MAX1003
_______________Detailed Description
Converter Operation
The MAX1003 contains two 6-bit analog-to-digital con-
verters (ADCs), a buffered voltage reference, and oscil-
lator circuitry. The ADCs use a flash conversion
technique to convert an analog input signal into a 6-bit
parallel digital output code. The MAX1003’s unique
design includes 63 fully differential comparators and a
proprietary encoding scheme that ensures no more
than 1LSB dynamic encoding error. The control logic
interfaces easily to most digital signal processors
(DSPs) and microprocessors (µPs) with +3.3V CMOS-
compatible logic interfaces. Figure 1 shows the
MAX1003 in a typical application.
Programmable Input Amplifiers
The MAX1003 has two (I and Q) programmable-gain
input amplifiers with a -0.5dB bandwidth of 55MHz and
true differential inputs. To maximize performance in
high-speed systems, each amplifier has less than 5pF
of input capacitance. The input amplifier gain is pro-
grammed, via the GAIN pin, to provide three possible
input full-scale ranges (FSRs) as shown in Table 1.
Table 1. Input Amplifier Programming
GAIN
GND
Open
V
CC
INPUT FULL-SCALE RANGE
(mVp-p)
500
250
125
5
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