19-1486; Rev 0; 7/99
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
General Description
The MAX106 PECL-compatible, 600Msps, 8-bit analog-to-
digital converter (ADC) allows accurate digitizing of ana-
log signals with bandwidths to 2.2GHz. Fabricated on
Maxim’s proprietary advanced GST-2 bipolar process, the
MAX106 integrates a high-performance track/hold (T/H)
amplifier and a quantizer on a single monolithic die.
The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high, 7.6 effective bits performance at the
Nyquist frequency. A fully differential comparator design
and decoding circuitry combine to reduce out-of-
sequence code errors (thermometer bubbles or sparkle
codes) and provide excellent metastable performance of
one error per 10
27
clock cycles. Unlike other ADCs, which
can have errors that result in false full- or zero-scale out-
puts, the MAX106 limits the error magnitude to 1LSB.
The analog input is designed for either differential or sin-
gle-ended use with a ±250mV input voltage range. Dual,
differential, PECL-compatible output data paths ensure
easy interfacing and include an 8:16 demultiplexer feature
that reduces output data rates to one-half the sampling
clock rate. The PECL outputs can be operated from any
supply between +3V to +5V for compatibility with +3.3V or
+5V referenced systems. Control inputs are provided for
interleaving additional MAX106 devices to increase the
effective system sampling rate.
The MAX106 is packaged in a 25mm x 25mm, 192-con-
tact Enhanced Super-Ball-Grid Array (ESBGA™), and is
specified over the commercial (0°C to +70°C) temperature
range. For a pin-compatible higher speed upgrade, refer
to the MAX104 (1Gsps) and MAX108 (1.5Gsps) data
sheets.
o
600Msps Conversion Rate
o
2.2GHz Full-Power Analog Input Bandwidth
o
7.6 Effective Bits at f
IN
= 300MHz
(Nyquist frequency)
o
±0.25LSB INL and DNL
o
50Ω Differential Analog Inputs
o
±250mV Input Signal Range
o
On-Chip, +2.5V Precision Bandgap Voltage
Reference
o
Latched, Differential PECL Digital Outputs
o
Low Error Rate: 10
-27
Metastable States
o
Selectable 8:16 Demultiplexer
o
Internal Demux Reset Input with Reset Output
o
192-Contact ESBGA
o
Pin Compatible with Faster MAX104/MAX108
Features
MAX106
Ordering Information
PART
MAX106CHC
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
192 ESBGA
192-Contact ESBGA
Ball Assignment Matrix
TOP VIEW
Applications
Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
High-Energy Physics
Radar/ECM Systems
ATE Systems
MAX106
Typical Operating Circuit appears at end of data sheet.
ESBGA is a trademark of Amkor/Anam.
ESBGA
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
MAX106
ABSOLUTE MAXIMUM RATINGS
V
CC
A to GNDA .........................................................-0.3V to +6V
V
CC
D to GNDD.........................................................-0.3V to +6V
V
CC
I to GNDI ............................................................-0.3V to +6V
V
CC
O to GNDD ........................................-0.3V to (V
CC
D + 0.3V)
AUXEN1, AUXEN2 to GND .....................-0.3V to (V
CC
D + 0.3V)
V
EE
to GNDI..............................................................-6V to +0.3V
Between GNDs......................................................-0.3V to +0.3V
V
CC
A to V
CC
D .......................................................-0.3V to +0.3V
V
CC
A to V
CC
I.........................................................-0.3V to +0.3V
PECL Digital Output Current ...............................................50mA
REFIN to GNDR ........................................-0.3V to (V
CC
I + 0.3V)
REFOUT Current ................................................+100µA to -5mA
ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V
TTL/CMOS Control Inputs
(DEMUXEN, DIVSELECT) ....................-0.3V to (V
CC
D + 0.3V)
RSTIN+, RSTIN- ......................................-0.3V to (V
CC
O + 0.3V)
VOSADJ Adjust Input ................................-0.3V to (V
CC
I + 0.3V)
CLK+ to CLK- Voltage Difference..........................................±3V
CLK+, CLK-.....................................(V
EE
- 0.3V) to (GNDD + 1V)
CLKCOM.........................................(V
EE
- 0.3V) to (GNDD + 1V)
VIN+ to VIN- Voltage Difference ............................................±2V
VIN+, VIN- to GNDI................................................................±2V
Continuous Power Dissipation (T
A
= +70°C)
192-Contact ESBGA (derate 61mW/°C above +70°C) ...4.88W
(with heatsink and 200LFM airflow,
derate 106mW/°C above +70°C) ....................................8.48W
Operating Temperature Range
MAX106CHC........................................................0°C to +70°C
Operating Junction Temperature.....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
A = V
CC
I = V
CC
D = +5.0V ±5%, V
EE
= -5.0V ±5%, V
CC
O = +3.0V to V
CC
D, REFIN connected to REFOUT, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
ACCURACY
Resolution
Integral Nonlinearity (Note 1)
Differential Nonlinearity (Note 1)
Missing Codes
ANALOG INPUTS
Full-Scale Input Range (Note 1)
Common-Mode Input Range
Input Resistance
Input Resistance Temperature
Coefficient
V
OS
ADJUST CONTROL INPUT
Input Resistance (Note 2)
Input V
OS
Adjust Range
REFERENCE INPUT AND OUTPUT
Reference Output Voltage
Reference Output Load
Regulation
Reference Input Resistance
REFOUT
Driving REFIN input only
2.475
2.50
2.525
5
4
5
V
mV
kΩ
R
VOS
VOSADJ = 0 to 2.5V
14
±4
25
±5.5
kΩ
LSB
V
FSR
V
CM
R
IN
TC
R
Signal + offset w.r.t. GNDI
VIN+ and VIN- to GNDI, T
A
= +25°C
49
475
500
±0.8
50
150
51
525
mVp-p
V
Ω
ppm/°C
RES
INL
DNL
T
A
= +25° C
T
A
= +25° C
No missing codes guaranteed
8
-0.5
-0.5
±0.25
±0.25
0.5
0.5
None
Bits
LSB
LSB
Codes
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
∆REFOUT
0 < I
SOURCE
< 2.5mA
R
REF
Referenced to GNDR
2
_______________________________________________________________________________________
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V ±5%, V
EE
= -5.0V ±5%, V
CC
O = +3.0V to V
CC
D, REFIN connected to REFOUT, T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
CLOCK INPUTS
(Note 3)
Clock Input Resistance
Input Resistance Temperature
Coefficient
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
DEMUX RESET INPUT
(Note 4)
Digital Input High Voltage
Digital Input Low Voltage
PECL DIGITAL OUTPUTS
(Note 5)
Digital Output High Voltage
Digital Output Low Voltage
POWER REQUIREMENTS
Positive Analog Supply Current
Positive Input Supply Current
Negative Input Supply Current
Digital Supply Current
Output Supply Current (Note 6)
Power Dissipation (Note 6)
Common-Mode Rejection Ratio
(Note 7)
Positive Power-Supply Rejection
Ratio (Note 8)
Negative Power-Supply
Rejection Ratio (Note 8)
I
CCA
I
CCI
I
EE
I
CC
D
I
CC
O
P
DISS
CMRR
PSRR+
PSRR-
VIN+ = VIN- = ±0.1V
(Note 9)
(Note 10)
40
40
40
-290
480
108
-210
205
75
5.25
68
73
68
340
115
780
150
mA
mA
mA
mA
mA
W
dB
dB
dB
V
OH
V
OL
-1.025
-1.810
-0.880
-1.620
V
V
V
IH
V
IL
-1.165
-1.475
V
V
R
CLK
TC
R
CLK+ and CLK- to CLKCOM, T
A
= +25°C
48
50
150
52
Ω
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX106
TTL/CMOS CONTROL INPUTS
(DEMUXEN, DIVSELECT)
V
IH
V
IL
I
IH
I
IL
V
IH
= 2.4V
V
IL
= 0
-1
2.0
0.8
50
1
V
V
µA
µA
_______________________________________________________________________________________
3
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
MAX106
AC ELECTRICAL CHARACTERISTICS
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 600Msps, f
IN
at -1dBFS, T
A
= +25°C,
unless otherwise noted.)
PARAMETER
ANALOG INPUT
Analog Input Full-Power
Bandwidth
Analog Input VSWR
Transfer Curve Offset
DYNAMIC SPECIFICATIONS
ENOB
600
Effective Number of Bits
(Note 11)
ENOB
300
ENOB
125
SNR
600
Signal-to-Noise Ratio
(No Harmonics)
SNR
300
SNR
125
THD
600
Total Harmonic Distortion
(Note 12)
THD
300
THD
125
SFDR
600
Spurious-Free Dynamic
Range
SFDR
300
SFDR
125
SINAD
600
Signal-to-Noise Ratio and
Distortion (Note 11)
SINAD
300
SINAD
125
Two-Tone Intermodulation
IMD
f
IN
= 600MHz
f
IN
= 300MHz
f
IN
= 125MHz
f
IN
= 600MHz
f
IN
= 300MHz
f
IN
= 125MHz
f
IN
= 600MHz
f
IN
= 300MHz
f
IN
= 125MHz
f
IN
= 600MHz
f
IN
= 300MHz
f
IN
= 125MHz
f
IN
= 600Hz
f
IN
= 300MHz
f
IN
= 125MHz
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
Differential
Single-ended
46.3
45.7
63.0
52.0
-63.0
-52.0
44.2
43.8
7.4
7.3
7.63
7.62
7.65
7.65
7.74
7.74
46.8
46.8
47.1
47.1
47.4
47.4
-57.0
-56.1
-56.5
-56.5
-67.5
-67.5
57.4
56.7
57.5
57.4
69.9
69.9
47.7
47.6
47.8
47.8
48.4
48.4
-61.8
dB
dB
dB
dB
dB
Bits
BW
-3dB
VSWR
V
OS
f
IN
= 500MHz
VOSADJ control input open
-1.5
2.2
1.1:1
0
1.5
GHz
V/V
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
IN1
= 124MHz, f
IN2
= 126MHz,
at -7dB below full scale
4
_______________________________________________________________________________________
±5V, 600Msps, 8-Bit ADC with On-Chip
2.2GHz Bandwidth Track/Hold Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
A = V
CC
I = V
CC
D = +5.0V, V
EE
= -5.0V, V
CC
O = +3.3V, REFIN connected to REFOUT, f
S
= 600Msps, f
IN
at -1dBFS, T
A
= +25°C,
unless otherwise noted.)
PARAMETER
TIMING CHARACTERISTICS
Maximum Sample Rate
Clock Pulse Width Low
Clock Pulse Width High
Aperture Delay
Aperture Jitter
Reset Input Data Setup Time
(Note 13)
Reset Input Data Hold Time
(Note 13)
CLK to DREADY Propagation
Delay
DREADY to DATA Propagation
Delay (Note 14)
DATA Rise Time
DATA Fall Time
DREADY Rise Time
DREADY Fall Time
Primary Port Pipeline Delay
Auxiliary Port Pipeline Delay
f
MAX
t
PLW
t
PWH
t
AD
t
AJ
t
SU
t
HD
t
PD1
t
PD2
t
RDATA
t
FDATA
t
RDREADY
t
FDREADY
t
PDP
t
PDA
Figure 17
Figure 17
Figure 17
Figure 4
Figure 15
Figure 15
Figure 17
Figure 17
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
20% to 80%, C
L
= 3pF
Figures 6, 7, 8
Figures 6, 7, 8
DIV1, DIV2 modes
DIV4 mode
DIV1, DIV2 modes
DIV4 mode
-50
0
0
2.2
150
420
360
220
180
7.5
7.5
8.5
9.5
350
600
0.75
0.75
100
< 0.5
5
Msps
ns
ns
ps
ps
ps
ps
ns
ps
ps
ps
ps
ps
Clock
Cycles
Clock
Cycles
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX106
Note 1:
Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256
·
slope of the line.
Note 2:
The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit
voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3:
The clock input’s termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings on
the CLK+ and CLK- inputs.
Note 4:
Input logic levels are measured with respect to the V
CC
O power-supply voltage.
Note 5:
All PECL digital outputs are loaded with 50Ω to V
CC
O - 2.0V. Measurements are made with respect to the V
CC
O power-
supply voltage.
Note 6:
The current in the V
CC
O power supply does not include the current in the digital output’s emitter followers, which is a func-
tion of the load resistance and the V
TT
termination voltage.
Note 7:
Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the
common-mode voltage, expressed in dB.
Note 8:
Measured with the positive supplies tied to the same potential, V
CC
A = V
CC
D = V
CC
I. V
CC
varies from +4.75V to +5.25V.
Note 9:
V
EE
varies from -5.25V to -4.75V.
Note 10:
Power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power
supply voltage, expressed in dB.
Note 11:
Effective number of bits (ENOB) and signal-to-noise plus distortion (SINAD) are computed from a curve fit referenced to the
theoretical full-scale range.
_______________________________________________________________________________________
5
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