19-2094; Rev 0; 7/01
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
General Description
The MAX1182 is a +3V, dual 10-bit analog-to-digital
converter (ADC) featuring fully-differential wideband
track-and-hold (T/H) inputs, driving two pipelined, 9-
stage ADCs. The MAX1182 is optimized for low-power,
high-dynamic performance applications in imaging,
instrumentation and digital communication applications.
This ADC operates from a single +2.7V to +3.6V sup-
ply, consuming only 195mW while delivering a typical
signal-to-noise ratio (SNR) of 59dB at an input frequen-
cy of 20MHz and a sampling rate of 65Msps. The T/H
driven input stages incorporate 400MHz (-3dB) input
amplifiers. The converters may also be operated with
single-ended inputs. In addition to low operating power,
the MAX1182 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.
An internal +2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of the internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1182 features parallel, CMOS-compatible
three-state outputs. The digital output format is set to
two’s complement or straight offset binary through a
single control pin. The device provides for a separate
output power supply of +1.7V to +3.6V for flexible inter-
facing. The MAX1182 is available in a 7mm x 7mm, 48-
pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible higher and lower speed versions of the
MAX1182 are also available. Please refer to the
MAX1180 datasheet for 105Msps, the MAX1181
datasheet for 80Msps, the MAX1183 datasheet for
40Msps, and the MAX1184 datasheet for 20Msps. In
addition to these speed grades, this family includes a
20Msps multiplexed output version (MAX1185), for
which digital data is presented time-interleaved on a
single, parallel 10-bit output port.
Features
o
Single +3V Operation
o
Excellent Dynamic Performance:
59dB SNR at f
IN
= 20MHz
77dB SFDR at f
IN
= 20MHz
o
Low Power:
65mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
o
0.02dB Gain and 0.25° Phase Matching (typ)
o
Wide ±1V
P-P
Differential Analog Input Voltage
Range
o
400MHz -3dB Input Bandwidth
o
On-Chip +2.048V Precision Bandgap Reference
o
User-Selectable Output Format—Two’s
Complement or Offset Binary
o
48-Pin TQFP Package with Exposed Pad for
Improved Thermal Dissipation
o
Evaluation Kit Available
MAX1182
Ordering Information
PART
MAX1182ECM
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
48 TQFP-EP
Pin Configuration
REFN
REFP
REFIN
REFOUT
D9A
D8A
D7A
D6A
D5A
D4A
D3A
D2A
48
47
46
45
44
43
42
41
40
39
38
Applications
High Resolution Imaging
I/Q Channel Digitization
Multchannel IF Undersampling
Instrumentation
Video Application
COM
V
DD
GND
INA+
INA-
V
DD
GND
INB-
INB+
GND
V
DD
CLK
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
MAX1182
D1A
D0A
OGND
OV
DD
OV
DD
OGND
D0B
D1B
D2B
D3B
D4B
D5B
GND
V
DD
V
DD
GND
T/B
SLEEP
PD
48 TQFP-EP
________________________________________________________________
Maxim Integrated Products
OE
D9B
D8B
D7B
D6B
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
MAX1182
ABSOLUTE MAXIMUM RATINGS
V
DD
, OVDD to GND...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN, CLK,
COM to GND ..........................................-0.3V to (V
DD
+ 0.3V)
OE,
PD, SLEEP, T/B, D9A–D0A,
D9B–D0B to OGND .............................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C).......1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead temperature (soldering, 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +3V, OV
DD
= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10kΩ resistor, V
IN
= 2Vp-p (differential w.r.t. COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 65MHz (50% duty cycle),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT
Differential Input Voltage
Range
Common-Mode Input Voltage
Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS
(f
CLK
= 65MHz, 4096-point FFT)
f
INA or B
= 7.47MHz, T
A
= +25°C
Signal-to-Noise Ratio
SNR
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 39.9MHz (Note 1)
Signal-to-Noise and Distortion
(up to 5th harmonic)
f
INA or B
= 7.47MHz, T
A
= +25°C
SINAD
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 39.9MHz (Note 1)
f
INA or B
= 7.47MHz, T
A
= +25°C
Spurious-Free Dynamic Range
SFDR
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 39.9MHz, (Note 1)
65
65
56.5
56
56.8
56.5
59.5
59
59
59
58.5
58.5
76
77
75
dBc
dB
dB
f
CLK
65
5
MHz
Clock
Cycles
V
DIFF
V
CM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±1.0
V
DD
/2
±
0.5
33
5
V
V
kΩ
pF
INL
DNL
f
IN
= 7.47MHz
f
IN
= 7.47MHz, no missing codes guaranteed
10
±0.6
±0.4
<
±1
0
±1.9
±1.0
±1.7
±2
Bits
LSB
LSB
% FS
% FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3V, OV
DD
= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10kΩ resistor, V
IN
= 2Vp-p (differential w.r.t. COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 65MHz (50% duty cycle),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Third-Harmonic Distortion
Intermodulation Distortion
(first 5 odd-order IMDs)
Total Harmonic Distortion
(first 5 harmonics)
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
Differential Gain
Differential Phase
Output Noise
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
BUFFERED EXTERNAL REFERENCE
(V
REFIN
= +2.048V)
REFIN Input Voltage
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Differential Reference Output
Voltage Range
REFIN Resistance
V
REFIN
V
REFP
V
REFN
∆V
REF
R
REFIN
∆V
REF
= V
REFP
- V
REFN
0.98
2.048
2.012
0.988
1.024
>50
1.07
V
V
V
V
MΩ
REFOUT
TC
REF
2.048
±3%
60
1.25
V
ppm/°C
mV/mA
INA+ = INA- = INB+ = INB- = COM
FPBW
t
AD
t
AJ
For 1.5 x full-scale input
SYMBOL
HD3
CONDITIONS
f
INA or B
= 7.47MHz
f
INA or B
= 20MHz
f
INA or B
= 39.9MHz (Note 1)
IMD
f
INA or B
= 19.13042MHz at -6.5dB FS
f
INA or B
= 21.2886MHz at -6.5dB FS (Note 2)
f
INA or B
= 7.47MHz, T
A
= +25°C
THD
f
INA or B
= 20MHz, T
A
= +25°C
f
INA or B
= 39.9MHz, (Note 1)
Input at -20dB FS, differential inputs
Input at -0.5dB FS, differential inputs
MIN
TYP
-83
-82
-77
-75
-75.5
-76
-74
500
400
1
2
2
±1
±0.25
0.2
MHz
MHz
ns
ps
RMS
ns
%
degrees
LSB
RMS
-64
-63
dBc
dBc
dBc
MAX
UNITS
MAX1182
_______________________________________________________________________________________
3
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
MAX1182
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3V, OV
DD
= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10kΩ resistor, V
IN
= 2Vp-p (differential w.r.t. COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 65MHz (50% duty cycle),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink
Current
Maximum REFN Source Current
Maximum REFN Sink Current
SYMBOL
I
SOURCE
I
SINK
I
SOURCE
I
SINK
R
REFP
,
R
REFN
∆V
REF
V
COM
V
REFP
V
REFN
Measured between REFP and COM, and
REFN and COM
∆V
REF
= V
REFP
– V
REFN
CONDITIONS
MIN
TYP
>5
250
250
>5
MAX
UNITS
mA
µA
µA
mA
UNBUFFERED EXTERNAL REFERENCE
(V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
Differential Reference Input
Voltage
COM Input Voltage
REFP Input Voltage
REFN Input Voltage
4
1.024
±10%
VDD/2
±
10%
V
COM
+
∆V
REF
/2
V
COM
-
∆V
REF
/2
CLK
PD,
OE,
SLEEP, T/B
CLK
PD,
OE,
SLEEP, T/B
0.1
V
IH
= OV
DD
or V
DD
(CLK)
V
IL
= 0
5
I
SINK
= 200µA
I
SOURCE
= 200µA
OE
= OV
DD
OE
= OV
DD
5
OV
DD
- 0.2
±10
0.2
±5
±5
0.8 x V
DD
0.8 x OV
DD
0.2 x V
DD
0.2 x OV
DD
kΩ
V
V
V
V
DIGITAL INPUTS (CLK, PD,
OE
, SLEEP, T/B)
Input High Threshold
Input Low Threshold
Input Hysteresis
Input Leakage
Input Capacitance
V
IH
V
IL
V
HYST
I
IH
I
IL
C
IN
V
V
V
µA
pF
V
V
µA
pF
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
Output Voltage Low
V
OL
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
V
OH
I
LEAK
C
OUT
4
_______________________________________________________________________________________
Dual 10-Bit, 65Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
MAX1182
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3V, OV
DD
= +2.5V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through
a 10kΩ resistor, V
IN
= 2Vp-p (differential w.r.t. COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 65MHz (50% duty cycle),
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
V
DD
OV
DD
Operating, f
INA or B
= 20MHz at -0.5dB FS
I
VDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, C
L
= 15pF, f
INA or B
= 20MHz at
-0.5dB FS
Output Supply Current
I
OVDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA or B
= 20MHz at -0.5dB FS
Power Dissipation
PDISS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
t
DO
t
ENABLE
t
DISABLE
t
CH
t
CL
t
WAKE
Figure 3 (Note 3)
Figure 4
Figure 4
Figure 3, clock period: 15.4ns
Figure 3, clock period: 15.4ns
Wakeup from Sleep mode (Note 4)
Wakeup from Shutdown (Note 4)
f
INA or B
= 20MHz at -0.5dB FS
f
INA or B
= 20MHz at -0.5dB FS
f
INA or B
= 20MHz at -0.5dB FS
5
10
1.5
7.7
±
1.5
7.7
±
1.5
0.42
1.5
-70
0.02
0.25
±0.2
8
ns
ns
ns
ns
ns
µs
PSRR
Offset
Gain
2.7
1.7
3.0
2.5
65
2.8
1
11
100
2
195
8.4
3
±0.2
±0.1
45
10
240
15
3.6
3.6
80
V
V
mA
µA
mA
µA
mW
µW
mV/V
%/V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
dB
dB
degrees
Note 1:
SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a +1.024V full-scale
input voltage range.
Note 2:
Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 3:
Digital outputs settle to V
IH
, V
IL
. Parameter guaranteed by design.
Note 4:
With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5:
Equivalent dynamic performance is obtainable over full OV
DD
range with reduced C
L
.
_______________________________________________________________________________________
5
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