19-2600; Rev 0; 9/02
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
General Description
The MAX1196 is a 3V, dual 8-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1196
is optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumenta-
tion, and digital communications. This ADC operates
from a single 2.7V to 3.6V supply, consuming only
87mW while delivering a typical signal-to-noise and dis-
tortion (SINAD) of 48.4dB at an input frequency of
20MHz and a sampling rate of 40Msps. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters can also be operated with single-
ended inputs. In addition to low operating power, the
MAX1196 features a 3mA sleep mode as well as a
0.1µA power-down mode to conserve power during idle
periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired for applications requiring
increased accuracy or a different input voltage range.
The MAX1196 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output format
can be set to two’s complement or straight offset binary
through a single control pin. The device provides for a
separate output power supply of 1.7V to 3.6V for flexible
interfacing. The MAX1196 is available in a 7mm
×
7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible, nonmultiplexed higher speed versions of
the MAX1196 are also available. Refer to the MAX1198
data sheet for 100Msps, the MAX1197 data sheet for
60Msps, and the MAX1195 data sheet for 40Msps.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1186 data sheet. With the N.C. pins of the
MAX1196 internally pulled down to ground, this ADC
becomes a drop-in replacement for the MAX1186.
o
Single 2.7V to 3.6V Operation
o
Excellent Dynamic Performance
48.4dB/44.7dB SINAD at f
IN
= 20MHz/200MHz
68.9dB/53dBc SFDR at f
IN
= 20MHz/200MHz
o
-72dB Interchannel Crosstalk at f
IN
= 20MHz
o
Low Power
87mW (Normal Operation)
9mW (Sleep Mode)
0.3µW (Shutdown Mode)
o
0.05dB Gain and
±0.05°
Phase Matching
o
Wide
±1V
P-P
Differential Analog Input Voltage
Range
o
400MHz -3dB Input Bandwidth
o
On-Chip 2.048V Precision Bandgap Reference
o
User-Selectable Output Format—Two’s
Complement or Offset Binary
o
Pin-Compatible 8-Bit and 10-Bit Upgrades
Available
Features
MAX1196
Ordering Information
PART
TEMP RANGE
MAX1196ECM
-40°C to +85°C
*EP
= Exposed pad.
PIN-PACKAGE
48 TQFP-EP*
Pin Configuration
REFN
REFP
REFIN
REFOUT
D7A/B
D6A/B
D5A/B
D4A/B
D3A/B
D2A/B
D1A/B
D0A/B
48
47
46
45
44
43
42
41
40
39
38
Applications
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical Imaging
Battery-Powered Instrumentation
WLAN, WWAN, WLL, MMDS Modems
Set-Top Boxes
VSAT Terminals
Functional Diagram appears at end of data sheet.
COM
V
DD
GND
INA+
INA-
V
DD
GND
INB-
INB+
GND
V
DD
CLK
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
MAX1196
N.C.
N.C.
OGND
OV
DD
OV
DD
OGND
A/B
N.C.
N.C.
N.C.
N.C.
N.C.
GND
V
DD
V
DD
GND
T/B
SLEEP
PD
OE
N.C.
N.C.
N.C.
TQFP-EP
________________________________________________________________
Maxim Integrated Products
N.C.
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX1196
ABSOLUTE MAXIMUM RATINGS
V
DD
, OV
DD
to GND .............................................. -0.3V to +3.6V
OGND to GND...................................................... -0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN, COM,
CLK to GND............................................-0.3V to (V
DD
+ 0.3V)
OE,
PD, SLEEP, T/B,
D7A/B–D0A/B, A/B to OGND...............-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= OV
DD
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T
A
= +25°C.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Gain Temperature Coefficient
ANALOG INPUT
Differential Input Voltage Range
Common-Mode Input Voltage
Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS
(f
CLK
= 40MHz)
f
INA or B
= 2MHz at -1dB FS
Signal-to-Noise Ratio
SNR
f
INA or B
= 7.5MHz at -1dB FS
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 101MHz at -1dB FS
f
INA or B
= 2MHz at -1dB FS
Signal-to-Noise and Distortion
SINAD
f
INA or B
= 7.5MHz at -1dB FS
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 101MHz at -1dB FS
47
47.5
48.7
48.7
48.5
48
48.6
48.7
48.4
48
dB
dB
f
CLK
CHA
CHB
40
5
5.5
MHz
Clock
Cycles
V
DIFF
V
CM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±100
±1.0
V
DD
/ 2
±
0.2
140
5
INL
DNL
f
IN
= 7.51MHz (Note 1)
f
IN
= 7.51MHz, no missing codes
guaranteed (Note 1)
SYMBOL
CONDITIONS
MIN
8
±0.3
±0.15
±1
±1
±4
±4
TYP
MAX
UNITS
Bits
LSB
LSB
%FS
%FS
ppm/°C
V
V
kΩ
pF
2
_______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= OV
DD
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
f
INA or B
= 2MHz at -1dB FS
Spurious-Free Dynamic Range
SFDR
f
INA or B
= 7.5MHz at -1dB FS
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 101MHz at -1dB FS
f
INA or B
= 2MHz at -1dB FS
Third-Harmonic Distortion
HD3
f
INA or B
= 7.5MHz at -1dB FS
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 101MHz at -1dB FS
Intermodulation Distortion
(First Five Odd-Order IMDs) (Note 2)
Third-Order Intermodulation
Distortion (Note 2)
IMD
IM3
f
IN1(A or B)
= 1.997MHz at -7dB FS,
f
IN2(A or B)
= 2.046MHz at -7dB FS
f
IN1(A or B)
= 1.997MHz at -7dB FS,
f
IN2(A or B)
= 2.046MHz at -7dB FS
f
INA or B
= 2MHz at -1dB FS
Total Harmonic Distortion
(First Four Harmonics)
Small-Signal Bandwidth
Full-Power Bandwidth
Gain Flatness (12MHz Spacing)
(Note 3)
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
t
AD
t
AJ
1dB SNR degradation at Nyquist
For 1.5
×
full-scale input
FPBW
THD
f
INA or B
= 7.5MHz at -1dB FS
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 101MHz at -1dB FS
Input at -20dB FS, differential inputs
Input at -1dB FS, differential inputs
f
IN1(A or B)
= 106MHz at -1dB FS,
f
IN2(A or B)
= 118MHz at -1dB FS
60
MIN
TYP
69
70
68.9
65
-72
-73.7
-75
-67
-68
-73.2
-70
-69
-69
-63
500
400
0.05
1
2
2
2.048
±3%
2.012
0.988
V
DD
/ 2
±
0.1
1.024
±3%
±100
MHz
MHz
dB
ns
ps
RMS
ns
-57
dBc
dBc
dBc
dBc
dBc
MAX
UNITS
MAX1196
INTERNAL REFERENCE
(REFIN = REFOUT through 10kΩ resistor; REFP, REFN, and COM levels are generated internally.)
Reference Output Voltage
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Common-Mode Level
Differential Reference Output
Voltage Range
Reference Temperature
Coefficient
V
REFOUT
V
REFP
V
REFN
V
COM
∆V
REF
TC
REF
(Note 4)
(Note 5)
(Note 5)
(Note 5)
∆V
REF
= V
REFP
- V
REFN
V
V
V
V
V
ppm/°C
_______________________________________________________________________________________
3
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX1196
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= OV
DD
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T
A
= +25°C.)
PARAMETER
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Common-Mode Level
Differential Reference Output
Voltage Range
REFIN Resistance
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink Current
Maximum REFN Source Current
Maximum REFN Sink Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BUFFERED EXTERNAL REFERENCE
(V
REFIN
= 2.048V)
V
REFP
V
REFN
V
COM
∆V
REF
R
REFIN
I
SOURCE
I
SINK
I
SOURCE
I
SINK
R
REFP
,
R
REFN
C
IN
∆V
REF
V
COM
V
REFP
V
REFN
∆V
REF
= V
REFP
- V
REFN
(Note 5)
(Note 5)
(Note 5)
∆V
REF
= V
REFP
- V
REFN
2.012
0.988
V
DD
/ 2
±0.1
1.024
±2%
>50
5
-250
250
-5
V
V
V
V
MΩ
mA
µA
µA
mA
UNBUFFERED EXTERNAL REFERENCE
(V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
REFP, REFN, COM Input
Capacitance
Differential Reference Input
Voltage Range
COM Input Voltage Range
REFP Input Voltage
REFN Input Voltage
Measured between REFP and REFN
4
15
1.024
±10%
V
DD
/ 2
±5%
V
COM
+
∆V
REF
/ 2
V
COM
-
∆V
REF
/ 2
0.8
×
V
DD
0.8
×
OV
DD
0.2
×
V
DD
0.2
×
OV
DD
kΩ
pF
V
V
V
V
DIGITAL INPUTS
(CLK, PD,
OE,
SLEEP, T/B)
CLK
Input High Threshold
V
IH
PD,
OE,
SLEEP, T/B
CLK
Input Low Threshold
V
IL
PD,
OE,
SLEEP, T/B
V
V
4
_______________________________________________________________________________________
Dual 8-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= OV
DD
= 3V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10kΩ
resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs (Note 5), f
CLK
= 40MHz, T
A
= T
MIN
to T
MAX
,
unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values
are at T
A
= +25°C.)
PARAMETER
Input Hysteresis
Input Leakage
Input Capacitance
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
V
DD
OV
DD
Operating, f
INA&B
= 20MHz at -1dB FS
applied to both channels
Analog Supply Current
I
VDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA&B
= 20MHz at -1dB FS
applied to both channels (Note 6)
Output Supply Current
I
OVDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA&B
= 20MHz at -1dB FS
applied to both channels
Analog Power Dissipation
PDISS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
CLK Fall to CHB Output Data
Valid
Clock Rise/Fall to A/B Rise/Fall
Time
OE
Fall to Output Enable Time
OE
Rise to Output Disable Time
CLK Pulse Width High
t
DOA
t
DOB
t
DA/B
t
ENABLE
t
DISABLE
t
CH
Clock period: 25ns (Note 7)
C
L
= 20pF (Notes 1, 7)
C
L
= 20pF (Notes 1, 7)
6
6
6
5
5
12.5
±1.5
8.25
8.25
ns
ns
ns
ns
ns
ns
PSRR
Offset, V
DD
±5%
Gain, V
DD
±5%
2.7
1.7
3
3
29
3
0.1
8
3
3
87
9
0.3
±3
±3
60
µW
mV/V
10
108
20
µA
mA
µA
3.6
3.6
36
V
V
mA
SYMBOL
V
HYST
I
IH
I
IL
C
IN
V
OL
V
OH
I
LEAK
C
OUT
I
SINK
= -200µA
I
SOURCE
= 200µA
OE
= OV
DD
OE
= OV
DD
5
OV
DD
-
0.2
±10
V
IH
= V
DD
= OV
DD
V
IL
= 0
5
0.2
CONDITIONS
MIN
TYP
0.15
±20
±20
MAX
UNITS
V
µA
pF
V
V
µA
pF
MAX1196
DIGITAL OUTPUTS
(D0A/B–D7A/B, A/B)
mW
_______________________________________________________________________________________
5
FPGA/CPLD
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