19-2412; Rev 0; 4/02
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
General Description
The MAX1198 is a 3.3V, dual, 8-bit analog-to-digital con-
verter (ADC) featuring fully differential wideband track-
and-hold (T/H) inputs, driving two ADCs. The MAX1198
is optimized for low power, small size, and high-dynamic
performance for applications in imaging, instrumenta-
tion, and digital communications. This ADC operates
from a single 2.7V to 3.6V supply, consuming only
264mW, while delivering a typical signal-to-noise and
distortion (SINAD) of 48.1dB at an input frequency of
50MHz and a sampling rate of 100Msps. The T/H-driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1198 features a 3.2mA sleep mode, as well as a
0.15µA power-down mode to conserve power during
idle periods.
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
applied reference, if desired, for applications requiring
increased accuracy or a different input voltage range.
The MAX1198 features parallel, CMOS-compatible three-
state outputs. The digital output format can be set to two’s
complement or straight offset binary through a single con-
trol pin. The device provides for a separate output power
supply of 1.7V to 3.6V for flexible interfacing with various
logic families. The MAX1198 is available in a 7mm x 7mm,
48-pin TQFP package, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Pin-compatible lower speed versions of the MAX1198
are also available. Refer to the MAX1195 data sheet for
40Msps and the MAX1197 data sheet for 60Msps. In
addition to these speed grades, this family includes a
multiplexed output version (MAX1196, 40Msps), for
which digital data is presented time interleaved and on
a single, parallel 8-bit output port.
For a 10-bit, pin-compatible upgrade, refer to the
MAX1180 data sheet. With the N.C. pins of the
MAX1198 internally pulled down to ground, this ADC
becomes a drop-in replacement for the MAX1180.
o
Single 2.7V to 3.6V Operation
o
Excellent Dynamic Performance
48.1dB/47.6dB SINAD at f
IN
= 50MHz/200MHz
66dBc/61.5dBc SFDR at f
IN
= 50MHz/200MHz
o
-72dB Interchannel Crosstalk at f
IN
= 50MHz
o
Low Power
264mW (Normal Operation)
10.6mW (Sleep Mode)
0.5µW (Shutdown Mode)
o
0.05dB Gain and ±0.1° Phase Matching
o
Wide
±1V
P-P
Differential Analog Input Voltage
Range
o
400MHz -3dB Input Bandwidth
o
On-Chip 2.048V Precision Bandgap Reference
o
User-Selectable Output Format—Two’s
Complement or Offset Binary
o
Pin-Compatible 8-Bit and 10-Bit Upgrades
Available
Features
MAX1198
Ordering Information
PART
MAX1198ECM
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
48 TQFP-EP*
*EP
= Exposed paddle
Functional Diagram and Pin Compatible Upgrades table
appear at end of data sheet.
Pin Configuration
REFN
REFP
REFIN
REFOUT
D7A
D6A
D5A
D4A
D3A
D2A
D1A
D0A
48
47
46
45
44
43
42
41
40
39
38
Applications
Baseband I/Q Sampling
Multichannel IF Sampling
Ultrasound and Medical
Imaging
Battery-Powered
Instrumentation
WLAN, WWAN, WLL,
MMDS Modems
Set-Top Boxes
VSAT Terminals
COM
V
DD
GND
INA+
INA-
V
DD
GND
INB-
INB+
GND
V
DD
CLK
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
N.C.
N.C.
OGND
OV
DD
OV
DD
OGND
N.C.
N.C.
D0B
D1B
D2B
D3B
MAX1198
30
29
28
27
26
25
________________________________________________________________
Maxim Integrated Products
V
DD
V
DD
GND
T/B
SLEEP
PD
OE
D7B
D6B
D5B
D4B
GND
TQFP-EP
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
MAX1198
ABSOLUTE MAXIMUM RATINGS
V
DD
, OV
DD
to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
DD
REFIN, REFOUT, REFP, REFN,
COM, CLK to GND .................................-0.3V to (V
DD
+ 0.3V)
OE,
PD, SLEEP, T/B, D7A–D0A,
D7B–D0B to OGND .............................-0.3V to (OV
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C).........1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V, OV
DD
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Gain Temperature Coefficient
ANALOG INPUT
Differential Input Voltage Range
Common-Mode Input Voltage
Range
Input Resistance
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Data Latency
DYNAMIC CHARACTERISTICS
(f
CLK
= 100MHz, 4096-point FFT)
f
INA or B
= 7.5MHz at -1dB FS
Signal-to-Noise Ratio
SNR
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 50MHz at -1dB FS
f
INA or B
= 115.1MHz at -1dB FS
47.0
48.5
48.3
48.3
48.1
dB
f
CLK
100
5
MHz
Clock
Cycles
V
DIFF
V
CM
R
IN
C
IN
Switched capacitor load
Differential or single-ended inputs
±1.0
V
DD
/ 2
±0.2
57
5
V
V
kΩ
pF
±100
INL
DNL
f
IN
= 7.5MHz (Note 1)
f
IN
= 7.5MHz, no missing codes guaranteed
(Note 1)
8
±0.3
±0.2
±1
±1
±4
±4
Bits
LSB
LSB
%FS
%FS
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
f
INA or B
= 7.5MHz at -1dB FS
Signal-to-Noise and Distortion
SINAD
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 50MHz at -1dB FS
f
INA or B
= 115.1MHz at -1dB FS
f
INA or B
= 7.5MHz at -1dB FS
Spurious-Free Dynamic Range
SFDR
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 50MHz at -1dB FS
f
INA or B
= 115.1MHz at -1dB FS
f
INA or B
= 7.5MHz at -1dB FS
Third-Harmonic Distortion
HD3
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 50MHz at -1dB FS
f
INA or B
= 115.1MHz at -1dB FS
Intermodulation Distortion
(First Five Odd-Order IMDs)
Third-Order Intermodulation
Distortion
IMD
f
IN1(A or B)
= 1.989MHz at -7dB FS
f
IN2(A or B)
= 2.038MHz at -7dB FS
(Note 2)
f
IN1(A or B)
= 1.989MHz at -7dB FS
f
IN2(A or B)
= 2.038MHz at -7dB FS
(Note 2)
f
INA or B
= 7.5MHz at -1dB FS
Total Harmonic Distortion
(First Four Harmonics)
Small-Signal Bandwidth
Full-Power Bandwidth
Gain Flatness
(12MHz Spacing)
Aperture Delay
Aperture Jitter
Overdrive Recovery Time
t
AD
t
AJ
1dB SNR degradation at Nyquist
For 1.5
×
full-scale input
FPBW
THD
f
INA or B
= 20MHz at -1dB FS
f
INA or B
= 50MHz at -1dB FS
f
INA or B
= 115.1MHz at -1dB FS
Input at -20dB FS, differential inputs
Input at -1dB FS, differential inputs
f
IN1(A or B)
= 106MHz at -1dB FS
f
IN2(A or B)
= 118MHz at -1dB FS
(Note 3)
60
46.5
MIN
TYP
48.3
48.2
48.1
48
67
67
66
65
-67
-67
-67
-66
-69.5
dBc
dBc
dBc
dB
MAX
UNITS
MAX1198
IM3
-80
-66
-67
-64
-58
500
400
0.05
1
2
2
2.048
±3%
2.162
1.138
V
DD
/ 2
±0.1
-57
dBc
dBc
MHz
MHz
dB
ns
ps
RMS
ns
INTERNAL REFERENCE
(REFIN = REFOUT through 10kΩ resistor; REFP, REFN, and COM levels are generated internally.)
Reference Output Voltage
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Common-Mode Level
V
REFOUT
V
REFP
V
REFN
V
COM
(Note 4)
(Note 5)
(Note 5)
(Note 5)
V
V
V
V
_______________________________________________________________________________________
3
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
MAX1198
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
Differential Reference Output
Voltage Range
Reference Temperature
Coefficient
SYMBOL
∆V
REF
TC
REF
CONDITIONS
∆V
REF
= V
REFP
- V
REFN
MIN
TYP
1.024
±3%
±100
MAX
UNITS
V
ppm/°C
BUFFERED EXTERNAL REFERENCE
(V
REFIN
= 2.048V)
Positive Reference Output
Voltage
Negative Reference Output
Voltage
Common-Mode Level
Differential Reference Output
Voltage Range
REFIN Resistance
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink
Current
Maximum REFN Source Current
Maximum REFN Sink Current
V
REFP
V
REFN
V
COM
∆V
REF
R
REFIN
I
SOURCE
I
SINK
I
SOURCE
I
SINK
R
REFP
,
R
REFN
C
IN
∆V
REF
V
COM
V
REFP
V
REFN
∆V
REF
= V
REFP
- V
REFN
Measured between REFP, COM, REFN,
and COM
(Note 5)
(Note 5)
(Note 5)
∆V
REF
= V
REFP
- V
REFN
2.162
1.138
V
DD
/ 2
±0.1
1.024
±2%
>50
5
-250
250
-5
V
V
V
V
MΩ
mA
µA
µA
mA
UNBUFFERED EXTERNAL REFERENCE
(V
REFIN
= AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
REFP, REFN, COM Input
Capacitance
Differential Reference Input
Voltage Range
COM Input Voltage Range
REFP Input Voltage
REFN Input Voltage
4
15
1.024
±10%
V
DD
/ 2
±5%
V
COM
+
∆V
REF
/ 2
V
COM
-
∆V
REF
/ 2
0.8
×
V
DD
0.8
×
OV
DD
kΩ
pF
V
V
V
V
DIGITAL INPUTS
(CLK, PD,
OE,
SLEEP, T/B)
CLK
Input High Threshold
V
IH
PD,
OE,
SLEEP, T/B
V
4
_______________________________________________________________________________________
Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.3V, OV
DD
= 2.5V, 0.1µF and 2.2µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10kΩ resistor, V
IN
= 2V
P-P
(differential with respect to COM), C
L
= 10pF at digital outputs, f
CLK
= 100MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and characterization. Typical values are at
T
A
= +25°C.)
PARAMETER
SYMBOL
CLK
Input Low Threshold
V
IL
PD,
OE,
SLEEP, T/B
Input Hysteresis
Input Leakage
Input Capacitance
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
V
DD
OV
DD
C
L
= 15pF
Operating, f
INA & B
= 20MHz at -1dB FS
applied to both channels
Analog Supply Current
I
VDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA & B
= 20MHz at -1dB FS
applied to both channels (Note 6)
Output Supply Current
I
OVDD
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Operating, f
INA & B
= 20MHz at -1dB FS
applied to both channels
Analog Power Dissipation
PDISS
Sleep mode
Shutdown, clock idle, PD =
OE
= OV
DD
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
OE
Fall to Output Enable Time
OE
Rise to Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
t
DO
t
ENABLE
t
DISABLE
t
CH
t
CL
Clock period: 10ns (Note 7)
Clock period: 10ns (Note 7)
C
L
= 20pF (Notes 1, 7)
6
5
5
5 ±0.5
5 ±0.5
8.25
ns
ns
ns
ns
ns
PSRR
Offset, V
DD
±5%
Gain, V
DD
±5%
2.7
1.7
3.3
2.5
80
3.2
0.15
11.5
2
2
264
10.6
0.5
±3
±3
66
µW
mV/V
10
314
20
µA
mA
µA
3.6
3.6
95
V
V
mA
V
HYST
I
IH
I
IL
C
IN
V
OL
V
OH
I
LEAK
C
OUT
I
SINK
= -200µA
I
SOURCE
= 200µA
OE
= OV
DD
OE
= OV
DD
5
OV
DD
-
0.2
±10
V
IH
= V
DD
= OV
DD
V
IL
= 0
5
0.2
0.15
±20
±20
CONDITIONS
MIN
TYP
MAX
0.2
×
V
DD
0.2
×
OV
DD
UNITS
MAX1198
V
V
µA
pF
V
V
µA
pF
DIGITAL OUTPUTS
( D7A–D0A, D7B–D0B)
mW
_______________________________________________________________________________________
5
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